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Searched +full:0 +full:x20020000 (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_default.h26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
34 #define mmPCIE_INDEX_DEFAULT 0x00000000
35 #define mmPCIE_DATA_DEFAULT 0x00000000
36 #define mmPCIE_INDEX2_DEFAULT 0x00000000
37 #define mmPCIE_DATA2_DEFAULT 0x00000000
38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
[all …]
H A Dnbio_7_0_default.h26 #define cfgNB_NBCFG0_NB_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgNB_NBCFG0_NB_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgNB_NBCFG0_NB_COMMAND_DEFAULT 0x00000000
29 #define cfgNB_NBCFG0_NB_STATUS_DEFAULT 0x00000000
30 #define cfgNB_NBCFG0_NB_REVISION_ID_DEFAULT 0x00000000
31 #define cfgNB_NBCFG0_NB_REGPROG_INF_DEFAULT 0x00000000
32 #define cfgNB_NBCFG0_NB_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgNB_NBCFG0_NB_BASE_CODE_DEFAULT 0x00000000
34 #define cfgNB_NBCFG0_NB_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgNB_NBCFG0_NB_LATENCY_DEFAULT 0x00000000
[all …]
H A Dnbio_6_1_default.h26 #define cfgPSWUSCFG0_VENDOR_ID_DEFAULT 0x00000000
27 #define cfgPSWUSCFG0_DEVICE_ID_DEFAULT 0x00000000
28 #define cfgPSWUSCFG0_COMMAND_DEFAULT 0x00000000
29 #define cfgPSWUSCFG0_STATUS_DEFAULT 0x00000000
30 #define cfgPSWUSCFG0_REVISION_ID_DEFAULT 0x00000000
31 #define cfgPSWUSCFG0_PROG_INTERFACE_DEFAULT 0x00000000
32 #define cfgPSWUSCFG0_SUB_CLASS_DEFAULT 0x00000000
33 #define cfgPSWUSCFG0_BASE_CLASS_DEFAULT 0x00000000
34 #define cfgPSWUSCFG0_CACHE_LINE_DEFAULT 0x00000000
35 #define cfgPSWUSCFG0_LATENCY_DEFAULT 0x00000000
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-slc.txt29 reg = <0x20020000 0x1000>;
46 reg = <0x00000000 0x00064000>;
/linux/arch/arm/mach-lpc32xx/
H A Dphy3250.c47 .slave_channels = &pl08x_slave_channels[0],
64 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
65 OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
67 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
88 .atag_offset = 0x100,
H A Dlpc32xx.h17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
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/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-cti.yaml80 pattern: "^cti(@[0-9a-f]+)$"
122 const: 0
128 '^trig-conns@([0-9]+)$':
246 reg = <0x20020000 0x1000>;
257 reg = <0x859000 0x1000>;
273 reg = <0x858000 0x1000>;
281 #size-cells = <0>;
283 trig-conns@0 {
284 reg = <0>;
301 arm,trig-in-sigs = <0 1>;
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/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc32xx.dtsi20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Djuno-base.dtsi12 reg = <0x0 0x2a810000 0x0 0x10000>;
16 ranges = <0 0x0 0x2a820000 0x20000>;
21 reg = <0x10000 0x10000>;
27 reg = <0x0 0x2b1f0000 0x0 0x1000>;
38 reg = <0x0 0x2b400000 0x0 0x10000>;
50 reg = <0x0 0x2b500000 0x0 0x10000>;
61 reg = <0x0 0x2b600000 0x0 0x10000>;
67 power-domains = <&scpi_devpd 0>;
72 reg = <0x0 0x2c010000 0 0x1000>,
73 <0x0 0x2c02f000 0 0x2000>,
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi30 #size-cells = <0>;
35 reg = <0xf00>;
47 reg = <0xf01>;
57 reg = <0xf02>;
67 reg = <0xf03>;
75 cpu0_opp_table: opp-table-0 {
131 #clock-cells = <0>;
141 reg = <0x100b0000 0x4000>;
148 pinctrl-0 = <&i2s1_bus>;
154 reg = <0x100c0000 0x4000>;
[all …]
/linux/net/ipv6/
H A Dsit.c63 #define HASH(addr) (((__force u32)addr^((__force u32)addr>>4))&0xF)
106 int ifindex = dev ? dev->ifindex : 0; in ipip6_tunnel_lookup()
130 t = rcu_dereference(sitn->tunnels_wc[0]); in ipip6_tunnel_lookup()
141 unsigned int h = 0; in __ipip6_bucket()
142 int prio = 0; in __ipip6_bucket()
190 ipv6_addr_set(&t->ip6rd.prefix, htonl(0x20020000), 0, 0, 0); in ipip6_tunnel_clone_6rd()
191 t->ip6rd.relay_prefix = 0; in ipip6_tunnel_clone_6rd()
193 t->ip6rd.relay_prefixlen = 0; in ipip6_tunnel_clone_6rd()
217 if (err < 0) in ipip6_tunnel_create()
223 return 0; in ipip6_tunnel_create()
[all …]
/linux/arch/arc/net/
H A Dbpf_jit_arcv2.c91 #define REG_LO(r) (bpf2arc[(r)][0])
110 ZZ_4_byte = 0,
126 AA_none = 0,
134 X_zero = 0,
140 CC_always = 0, /* condition is true all the time */
155 #define IN_U6_RANGE(x) ((x) <= (0x40 - 1) && (x) >= 0)
156 #define IN_S9_RANGE(x) ((x) <= (0x100 - 1) && (x) >= -0x100)
157 #define IN_S12_RANGE(x) ((x) <= (0x800 - 1) && (x) >= -0x800)
158 #define IN_S21_RANGE(x) ((x) <= (0x100000 - 1) && (x) >= -0x100000)
159 #define IN_S25_RANGE(x) ((x) <= (0x1000000 - 1) && (x) >= -0x1000000)
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_hsi.h17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
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H A Dbnx2x_main.c126 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
147 BCM57710 = 0,
286 { 0 }
412 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
414 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
420 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
422 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
430 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
432 "comp_addr [%x:%08x], comp_val 0x%08x\n", in bnx2x_dp_dmae()
438 DP(msglvl, "DMAE: opcode 0x%08x\n" in bnx2x_dp_dmae()
[all …]