Home
last modified time | relevance | path

Searched +full:0 +full:x20 (Results 1 – 25 of 1046) sorted by relevance

12345678910>>...42

/linux/sound/pci/hda/
H A Dideapad_s740_helper.c5 { 0x20, AC_VERB_SET_COEF_INDEX, 0x10 },
6 { 0x20, AC_VERB_SET_PROC_COEF, 0x0320 },
7 { 0x20, AC_VERB_SET_COEF_INDEX, 0x24 },
8 { 0x20, AC_VERB_SET_PROC_COEF, 0x0041 },
9 { 0x20, AC_VERB_SET_COEF_INDEX, 0x24 },
10 { 0x20, AC_VERB_SET_PROC_COEF, 0x0041 },
11 { 0x20, AC_VERB_SET_COEF_INDEX, 0x29 },
12 { 0x20, AC_VERB_SET_COEF_INDEX, 0x29 },
13 { 0x20, AC_VERB_SET_COEF_INDEX, 0x26 },
14 { 0x20, AC_VERB_SET_PROC_COEF, 0x0000 },
[all …]
/linux/drivers/video/fbdev/sis/
H A Doem300.h55 {0x08,0x08,0x08,0x08},
56 {0x08,0x08,0x08,0x08},
57 {0x08,0x08,0x08,0x08},
58 {0x2c,0x2c,0x2c,0x2c},
59 {0x08,0x08,0x08,0x08},
60 {0x08,0x08,0x08,0x08},
61 {0x08,0x08,0x08,0x08},
62 {0x20,0x20,0x20,0x20}
67 {0x20,0x20,0x20,0x20},
68 {0x20,0x20,0x20,0x20},
[all …]
/linux/include/linux/mlx5/
H A Dmlx5_ifc.h38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
[all …]
H A Dmlx5_ifc_vdpa.h8 MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE = 0x0,
9 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE = 0x1,
10 MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE = 0x2,
14 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT = 0,
26 u8 virtio_q_type[0x8];
27 u8 reserved_at_8[0x5];
28 u8 event_mode[0x3];
29 u8 queue_index[0x10];
31 u8 full_emulation[0x1];
32 u8 virtio_version_1_0[0x1];
[all …]
H A Dmlx5_ifc_fpga.h36 u8 max_num_qps[0x10];
37 u8 reserved_at_10[0x8];
38 u8 total_rcv_credits[0x8];
40 u8 reserved_at_20[0xe];
41 u8 qp_type[0x2];
42 u8 reserved_at_30[0x5];
43 u8 rae[0x1];
44 u8 rwe[0x1];
45 u8 rre[0x1];
46 u8 reserved_at_38[0x4];
[all …]
/linux/drivers/hid/
H A Dhid-debug.c40 { 0x00, 0, "Undefined" },
41 { 0x01, 0, "GenericDesktop" },
42 { 0x01, 0x0001, "Pointer" },
43 { 0x01, 0x0002, "Mouse" },
44 { 0x01, 0x0004, "Joystick" },
45 { 0x01, 0x0005, "Gamepad" },
46 { 0x01, 0x0006, "Keyboard" },
47 { 0x01, 0x0007, "Keypad" },
48 { 0x01, 0x0008, "MultiaxisController" },
49 { 0x01, 0x0009, "TabletPCSystemControls" },
[all …]
/linux/kernel/bpf/preload/iterators/
H A Diterators.lskel-big-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
H A Diterators.lskel-little-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
/linux/lib/
H A Dmemcpy_kunit.c33 for (size_t i = 0; i < sizeof(instance.data); i++) { \
35 "line %d: '%s' not initialized to 0x%02x @ %zu (saw 0x%02x)\n", \
38 } while (0)
42 for (size_t i = 0; i < sizeof(one); i++) { \
44 "line %d: %s.data[%zu] (0x%02x) != %s.data[%zu] (0x%02x)\n", \
48 } while (0)
54 .data = { 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, in memcpy_test()
55 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, in memcpy_test()
56 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, in memcpy_test()
57 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, in memcpy_test()
[all …]
/linux/drivers/mtd/spi-nor/
H A Dmicron-st.c12 #define USE_FSR BIT(0)
14 #define SPINOR_OP_MT_DIE_ERASE 0xc4 /* Chip (die) erase opcode */
15 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
16 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
17 #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
18 #define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
19 #define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
20 #define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
21 #define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
22 #define SPINOR_REG_MT_CFR1V_DEF 0x1f /* Default dummy cycles */
[all …]
/linux/drivers/reset/
H A Dreset-ma35d1.c32 [MA35D1_RESET_CHIP] = {0x20, 0},
33 [MA35D1_RESET_CA35CR0] = {0x20, 1},
34 [MA35D1_RESET_CA35CR1] = {0x20, 2},
35 [MA35D1_RESET_CM4] = {0x20, 3},
36 [MA35D1_RESET_PDMA0] = {0x20, 4},
37 [MA35D1_RESET_PDMA1] = {0x20, 5},
38 [MA35D1_RESET_PDMA2] = {0x20, 6},
39 [MA35D1_RESET_PDMA3] = {0x20, 7},
40 [MA35D1_RESET_DISP] = {0x20, 9},
41 [MA35D1_RESET_VCAP0] = {0x20, 10},
[all …]
/linux/drivers/staging/media/meson/vdec/
H A Dcodec_h264.c15 #define SIZE_WORKSPACE 0x1ee000
22 #define WORKSPACE_BUF_OFFSET 0x1000000
25 #define CMD_MASK GENMASK(7, 0)
43 #define PIC_STRUCT_MASK GENMASK(2, 0)
44 #define BUF_IDX_MASK GENMASK(4, 0)
47 #define OFFSET_MASK GENMASK(15, 0)
51 #define MB_TOTAL_MASK GENMASK(15, 0)
52 #define MB_WIDTH_MASK GENMASK(7, 0)
54 #define MAX_REF_MASK GENMASK(6, 0)
56 #define AR_IDC_MASK GENMASK(7, 0)
[all …]
/linux/drivers/net/ethernet/microchip/
H A Denc28j60_hw.h15 * - Register address (bits 0-4)
19 #define ADDR_MASK 0x1F
20 #define BANK_MASK 0x60
21 #define SPRD_MASK 0x80
23 #define EIE 0x1B
24 #define EIR 0x1C
25 #define ESTAT 0x1D
26 #define ECON2 0x1E
27 #define ECON1 0x1F
28 /* Bank 0 registers */
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic79xx_reg_print.c_shipped12 { "SPLTINT", 0x01, 0x01 },
13 { "CMDCMPLT", 0x02, 0x02 },
14 { "SEQINT", 0x04, 0x04 },
15 { "SCSIINT", 0x08, 0x08 },
16 { "PCIINT", 0x10, 0x10 },
17 { "SWTMINT", 0x20, 0x20 },
18 { "BRKADRINT", 0x40, 0x40 },
19 { "HWERRINT", 0x80, 0x80 },
20 { "INT_PEND", 0xff, 0xff }
27 0x01, regvalue, cur_col, wrap));
[all …]
H A Daic7xxx_reg_print.c_shipped12 { "SCSIRSTO", 0x01, 0x01 },
13 { "ENAUTOATNP", 0x02, 0x02 },
14 { "ENAUTOATNI", 0x04, 0x04 },
15 { "ENAUTOATNO", 0x08, 0x08 },
16 { "ENRSELI", 0x10, 0x10 },
17 { "ENSELI", 0x20, 0x20 },
18 { "ENSELO", 0x40, 0x40 },
19 { "TEMODE", 0x80, 0x80 }
26 0x00, regvalue, cur_col, wrap));
30 { "CLRCHN", 0x02, 0x02 },
[all …]
H A Daic7xxx_reg.h_shipped19 ahc_print_register(NULL, 0, "SCSISEQ", 0x00, regvalue, cur_col, wrap)
26 ahc_print_register(NULL, 0, "SXFRCTL0", 0x01, regvalue, cur_col, wrap)
33 ahc_print_register(NULL, 0, "SCSISIGI", 0x03, regvalue, cur_col, wrap)
40 ahc_print_register(NULL, 0, "SCSIRATE", 0x04, regvalue, cur_col, wrap)
47 ahc_print_register(NULL, 0, "SSTAT0", 0x0b, regvalue, cur_col, wrap)
54 ahc_print_register(NULL, 0, "SSTAT1", 0x0c, regvalue, cur_col, wrap)
61 ahc_print_register(NULL, 0, "SSTAT2", 0x0d, regvalue, cur_col, wrap)
68 ahc_print_register(NULL, 0, "SSTAT3", 0x0e, regvalue, cur_col, wrap)
75 ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap)
82 ahc_print_register(NULL, 0, "SIMODE1", 0x11, regvalue, cur_col, wrap)
[all …]
H A Daic79xx_reg.h_shipped19 ahd_print_register(NULL, 0, "INTSTAT", 0x01, regvalue, cur_col, wrap)
26 ahd_print_register(NULL, 0, "HS_MAILBOX", 0x0b, regvalue, cur_col, wrap)
33 ahd_print_register(NULL, 0, "SEQINTSTAT", 0x0c, regvalue, cur_col, wrap)
40 ahd_print_register(NULL, 0, "INTCTL", 0x18, regvalue, cur_col, wrap)
47 ahd_print_register(NULL, 0, "DFCNTRL", 0x19, regvalue, cur_col, wrap)
54 ahd_print_register(NULL, 0, "DFSTATUS", 0x1a, regvalue, cur_col, wrap)
61 ahd_print_register(NULL, 0, "SG_CACHE_SHADOW", 0x1b, regvalue, cur_col, wrap)
68 ahd_print_register(NULL, 0, "SCSISEQ0", 0x3a, regvalue, cur_col, wrap)
75 ahd_print_register(NULL, 0, "SCSISEQ1", 0x3b, regvalue, cur_col, wrap)
82 ahd_print_register(NULL, 0, "DFFSTAT", 0x3f, regvalue, cur_col, wrap)
[all …]
/linux/include/dt-bindings/clock/
H A Domap4.h8 #define OMAP4_CLKCTRL_OFFSET 0x20
12 #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
15 #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
18 #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
19 #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
20 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
21 #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
22 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
23 #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
24 #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
[all …]
H A Domap5.h8 #define OMAP5_CLKCTRL_OFFSET 0x20
12 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
15 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
18 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
19 #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
20 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
21 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
22 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
23 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
24 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
[all …]
H A Ddra7.h8 #define DRA7_CLKCTRL_OFFSET 0x20
12 #define DRA7_MPU_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
15 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
18 #define DRA7_IPU1_MMU_IPU1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20)
21 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
23 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
24 #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
25 #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
26 #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
27 #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
[all …]
/linux/tools/testing/selftests/bpf/
H A Dip_check_defrag_frags.h10 0x45, 0x0, 0x0, 0x2c, 0x0, 0x1, 0x20, 0x0, 0x40, 0x11,
11 0xac, 0xe8, 0x0, 0x0, 0x0, 0x0, 0xac, 0x10, 0x1, 0xc8,
12 0xbe, 0xee, 0xbe, 0xef, 0x0, 0x3a, 0x0, 0x0, 0x54, 0x48,
13 0x49, 0x53, 0x20, 0x49, 0x53, 0x20, 0x54, 0x48, 0x45, 0x20,
14 0x4f, 0x52, 0x49, 0x47,
17 0x45, 0x0, 0x0, 0x2c, 0x0, 0x1, 0x20, 0x3, 0x40, 0x11,
18 0xac, 0xe5, 0x0, 0x0, 0x0, 0x0, 0xac, 0x10, 0x1, 0xc8,
19 0x49, 0x4e, 0x41, 0x4c, 0x20, 0x4d, 0x45, 0x53, 0x53, 0x41,
20 0x47, 0x45, 0x2c, 0x20, 0x50, 0x4c, 0x45, 0x41, 0x53, 0x45,
21 0x20, 0x52, 0x45, 0x41,
[all …]
/linux/drivers/gpu/drm/tests/
H A Ddrm_kunit_edid.h10 * 00 21 01 03 81 a0 5a 78 0a 00 00 00 00 00 00 00
14 * 74 20 45 44 49 44 0a 20 20 20 00 00 00 fd 00 32
15 * 46 1e 46 0f 00 0a 20 20 20 20 20 20 00 00 00 10
20 * Block 0, Base EDID:
48 * Checksum: 0xab
51 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x31, 0xd8, 0x2a, 0x00,
52 0x00, 0x00, 0x00, 0x00, 0x00, 0x21, 0x01, 0x03, 0x81, 0xa0, 0x5a, 0x78,
53 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
54 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
55 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a, 0x80, 0x18, 0x71, 0x38,
[all …]
/linux/drivers/isdn/hardware/mISDN/
H A Dhfc_multi.h6 #define DEBUG_HFCMULTI_FIFO 0x00010000
7 #define DEBUG_HFCMULTI_CRC 0x00020000
8 #define DEBUG_HFCMULTI_INIT 0x00040000
9 #define DEBUG_HFCMULTI_PLXSD 0x00080000
10 #define DEBUG_HFCMULTI_MODE 0x00100000
11 #define DEBUG_HFCMULTI_MSG 0x00200000
12 #define DEBUG_HFCMULTI_STATE 0x00400000
13 #define DEBUG_HFCMULTI_FILL 0x00800000
14 #define DEBUG_HFCMULTI_SYNC 0x01000000
15 #define DEBUG_HFCMULTI_DTMF 0x02000000
[all …]
/linux/drivers/media/i2c/
H A Dimx319.c14 #define IMX319_REG_MODE_SELECT 0x0100
15 #define IMX319_MODE_STANDBY 0x00
16 #define IMX319_MODE_STREAMING 0x01
19 #define IMX319_REG_CHIP_ID 0x0016
20 #define IMX319_CHIP_ID 0x0319
23 #define IMX319_REG_FLL 0x0340
24 #define IMX319_FLL_MAX 0xffff
27 #define IMX319_REG_EXPOSURE 0x0202
30 #define IMX319_EXPOSURE_DEFAULT 0x04f6
35 * | [7:0] | [15:8] |
[all …]
/linux/drivers/tty/serial/
H A Dsunsab.h11 u8 rfifo[0x20]; /* Receive FIFO */
24 u8 ccr0; /* Channel Configuration Register 0 */
33 u8 isr0; /* Interrupt Status 0 */
42 u8 xfifo[0x20]; /* Transmit FIFO */
69 u8 imr0; /* Interrupt Mask Register 0 */
78 u8 __pad1[0x20];
128 #define SAB82532_ALLS 0x00000001
129 #define SAB82532_XPR 0x00000002
130 #define SAB82532_REGS_PENDING 0x00000004
133 #define SAB82532_RSTAT_PE 0x80
[all …]

12345678910>>...42