Home
last modified time | relevance | path

Searched +full:0 +full:x1ff80 (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu8.h65 #define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF80
66 #define SMU8_UNBCSR_START_ADDR 0xC0100000
68 #define SMN_MP1_SRAM_START_ADDR 0x10000000
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b.dtsi19 #size-cells = <0>;
25 reg = <0x200>;
37 reg = <0x201>;
49 reg = <0x202>;
61 reg = <0x203>;
169 hwrom@0 {
170 reg = <0x0 0x200000>;
225 reg = <0xc8000000 0x8000>;
228 ranges = <0x0 0xc8000000 0x8000>;
232 reg = <0x400 0x20>;
[all …]
H A Dmeson8.dtsi21 #size-cells = <0>;
27 reg = <0x200>;
39 reg = <0x201>;
51 reg = <0x202>;
63 reg = <0x203>;
177 hwrom@0 {
178 reg = <0x0 0x200000>;
193 reg = <0x4f00000 0x100000>;
248 reg = <0xc8000000 0x8000>;
251 ranges = <0x0 0xc8000000 0x8000>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]