Searched +full:0 +full:x1ff80 (Results 1 – 4 of 4) sorted by relevance
65 #define SMU8_FIRMWARE_HEADER_LOCATION 0x1FF8066 #define SMU8_UNBCSR_START_ADDR 0xC010000068 #define SMN_MP1_SRAM_START_ADDR 0x10000000
27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x128 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x029 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x230 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x131 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x432 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x233 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x834 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x335 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x1036 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4[all …]
35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()39 while ((data & BIT_0) == 0) { in qla2x00_lock_nvram_access()42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()60 wrt_reg_word(®->u.isp2300.host_semaphore, 0); in qla2x00_unlock_nvram_access()98 * Bit 15-0 = write data107 uint16_t data = 0; in qla2x00_nvram_request()112 for (cnt = 0; cnt < 11; cnt++) { in qla2x00_nvram_request()116 qla2x00_nv_write(ha, 0); in qla2x00_nvram_request()121 for (cnt = 0; cnt < 16; cnt++) { in qla2x00_nvram_request()194 qla2x00_nv_write(ha, 0); in qla2x00_write_nvram_word()[all …]