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/linux/include/net/
H A Dieee80211_radiotap.h29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130.dtsi29 #define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
30 0xe0000000 + ((iface - 1) * 0x1000000))
31 #define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Du-boot.yaml43 partition@0 {
45 reg = <0x0 0x100000>;
53 reg = <0x100000 0x1ff00000>;
H A Dlinux,ubi.yaml47 partition@0 {
48 reg = <0x0 0x100000>;
54 reg = <0x100000 0x1ff00000>;
68 eeprom@0 {
69 reg = <0x0 0x1000>;
/linux/arch/sh/drivers/pci/
H A Dpci-sh7780.c24 # define PCICR_ENDIANNESS 0
31 .start = 0x1000,
35 .name = "PCI MEM 0",
36 .start = 0xfd000000,
37 .end = 0xfd000000 + SZ_16M - 1,
41 .start = 0x10000000,
42 .end = 0x10000000 + SZ_64M - 1,
49 .start = 0xc0000000,
50 .end = 0xc0000000 + SZ_512M - 1,
59 .io_offset = 0,
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sa8255p.yaml26 no "bus-range" is specified, this will be bus 0 (the default).
81 reg = <0x4 0x00000000 0 0x10000000>;
85 ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
86 <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
87 bus-range = <0x00 0xff>;
89 linux,pci-domain = <0>;
90 power-domains = <&scmi5_pd 0>;
91 iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
92 <0x100 &pcie_smmu 0x0001 0x1>;
106 interrupt-map-mask = <0 0 0 0x7>;
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.h19 #define AR_PHY_TEST 0x9800
20 #define PHY_AGC_CLR 0x10000000
21 #define RFSILENT_BB 0x00002000
23 #define AR_PHY_TURBO 0x9804
24 #define AR_PHY_FC_TURBO_MODE 0x00000001
25 #define AR_PHY_FC_TURBO_SHORT 0x00000002
26 #define AR_PHY_FC_DYN2040_EN 0x00000004
27 #define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28 #define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
30 #define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
[all …]
H A Dar9003_phy.c27 #define AR9300_11NA_OFDM_SHIFT 0
38 /* level: 0 1 2 3 4 5 6 7 8 */
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
42 /* level: 0 1 2 3 4 5 6 7 8 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
138 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
142 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
146 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
151 u16 bMode, fracMode = 0, aModeRefSel = 0; in ar9003_hw_set_channel()
152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel()
[all …]
/linux/arch/mips/sni/
H A Da20r.c30 PORT(0x3f8, 4),
31 PORT(0x2f8, 3),
45 .start = 0x1c081ffc,
46 .end = 0x1c081fff,
59 .start = 0x18000000,
60 .end = 0x18000004,
64 .start = 0x18010000,
65 .end = 0x18010004,
69 .start = 0x1ff00000,
70 .end = 0x1ff00020,
[all …]
H A Drm200.c37 MEMPORT(0x160003f8, RM200_I8259A_IRQ_BASE + 4),
38 MEMPORT(0x160002f8, RM200_I8259A_IRQ_BASE + 3),
52 .start = 0x1cd41ffc,
53 .end = 0x1cd41fff,
66 .start = 0x18000000,
67 .end = 0x180fffff,
71 .start = 0x1b000000,
72 .end = 0x1b000004,
76 .start = 0x1ff00000,
77 .end = 0x1ff00020,
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_hmmu0_mmu_masks.h24 #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_SHIFT 0
25 #define DCORE0_HMMU0_MMU_MMU_ENABLE_R_MASK 0x1
28 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_SHIFT 0
29 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_WEAK_ORDERING_MASK 0x1
31 #define DCORE0_HMMU0_MMU_FORCE_ORDERING_STRONG_ORDERING_MASK 0x2
34 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0
35 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1
37 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2
39 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4
41 #define DCORE0_HMMU0_MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8
[all …]
/linux/arch/mips/include/asm/
H A Dsni.h30 #define SNI_CPU_M8021 0x01
31 #define SNI_CPU_M8030 0x04
32 #define SNI_CPU_M8031 0x06
33 #define SNI_CPU_M8034 0x0f
34 #define SNI_CPU_M8037 0x07
35 #define SNI_CPU_M8040 0x05
36 #define SNI_CPU_M8043 0x09
37 #define SNI_CPU_M8050 0x0b
38 #define SNI_CPU_M8053 0x0d
40 #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000)
[all …]
/linux/arch/mips/include/asm/mach-loongson64/
H A Dloongson.h62 for (x = 0; x < 100000; x++) \
75 #define LOONGSON_FLASH_BASE 0x1c000000
76 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
79 #define LOONGSON_LIO0_BASE 0x1e000000
80 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
83 #define LOONGSON_BOOT_BASE 0x1fc00000
84 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
86 #define LOONGSON_REG_BASE 0x1fe00000
87 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
90 #define LOONGSON3_REG_BASE 0x3ff00000
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8992-lg-bullhead.dtsi26 qcom,msm-id = <251 0>, <252 0>;
27 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
47 reg = <0x0 0x1ff00000 0x0 0x40000>;
48 console-size = <0x10000>;
49 record-size = <0x10000>;
50 ftrace-size = <0x10000>;
51 pmsg-size = <0x20000>;
55 reg = <0 0x03400000 0 0xc00000>;
60 reg = <0x0 0x05000000 0x0 0x1a00000>;
71 pm8994_regulators: regulators-0 {
/linux/arch/mips/include/asm/mach-loongson2ef/
H A Dloongson.h60 for (x = 0; x < 100000; x++) \
69 #define LOONGSON_FLASH_BASE 0x1c000000
70 #define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
73 #define LOONGSON_LIO0_BASE 0x1e000000
74 #define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
77 #define LOONGSON_BOOT_BASE 0x1fc00000
78 #define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
80 #define LOONGSON_REG_BASE 0x1fe00000
81 #define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
84 #define LOONGSON_LIO1_BASE 0x1ff00000
[all …]
/linux/arch/mips/include/asm/mips-boards/
H A Dbonito64.h42 #define BONITO_BOOT_BASE 0x1fc00000
43 #define BONITO_BOOT_SIZE 0x00100000
45 #define BONITO_FLASH_BASE 0x1c000000
46 #define BONITO_FLASH_SIZE 0x03000000
48 #define BONITO_SOCKET_BASE 0x1f800000
49 #define BONITO_SOCKET_SIZE 0x00400000
51 #define BONITO_REG_BASE 0x1fe00000
52 #define BONITO_REG_SIZE 0x00040000
54 #define BONITO_DEV_BASE 0x1ff00000
55 #define BONITO_DEV_SIZE 0x00100000
[all …]
/linux/drivers/thermal/intel/
H A Dintel_pch_thermal.c22 #define PCH_THERMAL_DID_HSW_1 0x9C24 /* Haswell PCH */
23 #define PCH_THERMAL_DID_HSW_2 0x8C24 /* Haswell PCH */
24 #define PCH_THERMAL_DID_WPT 0x9CA4 /* Wildcat Point */
25 #define PCH_THERMAL_DID_SKL 0x9D31 /* Skylake PCH */
26 #define PCH_THERMAL_DID_SKL_H 0xA131 /* Skylake PCH 100 series */
27 #define PCH_THERMAL_DID_CNL 0x9Df9 /* CNL PCH */
28 #define PCH_THERMAL_DID_CNL_H 0xA379 /* CNL-H PCH */
29 #define PCH_THERMAL_DID_CNL_LP 0x02F9 /* CNL-LP PCH */
30 #define PCH_THERMAL_DID_CML_H 0X06F9 /* CML-H PCH */
31 #define PCH_THERMAL_DID_LWB 0xA1B1 /* Lewisburg PCH */
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250-monk.dts30 reg = <0x40000000 0x1ff00000>;
35 reg = <0x0205f000 0x1000>;
50 vemmc_reg: voltage-regulator-0 {
64 #size-cells = <0>;
70 reg = <0x25>;
150 io-channels = <&adc 0>;
195 #size-cells = <0>;
197 samsung,i2c-slave-addr = <0x10>;
205 reg = <0x66>;
217 regulator-name = "VAP_ALIVE_1.0V";
[all …]
H A Dexynos3250-rinato.dts36 reg = <0x40000000 0x1ff00000>;
41 reg = <0x0205f000 0x1000>;
66 #size-cells = <0>;
72 reg = <0x25>;
152 io-channels = <&adc 0>;
239 panel@0 {
241 reg = <0>;
253 cs-setup = <0>;
254 wr-setup = <0>;
256 wr-hold = <0>;
[all …]
/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
17 #define SSB_CHIPCO_CHIPID 0x0000
18 #define SSB_CHIPCO_IDMASK 0x0000FFFF
19 #define SSB_CHIPCO_REVMASK 0x000F0000
21 #define SSB_CHIPCO_PACKMASK 0x00F00000
23 #define SSB_CHIPCO_NRCORESMASK 0x0F000000
25 #define SSB_CHIPCO_CAP 0x0004 /* Capabilities */
26 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
27 #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
28 #define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h10 #define BCMA_CC_ID 0x0000
11 #define BCMA_CC_ID_ID 0x0000FFFF
12 #define BCMA_CC_ID_ID_SHIFT 0
13 #define BCMA_CC_ID_REV 0x000F0000
15 #define BCMA_CC_ID_PKG 0x00F00000
17 #define BCMA_CC_ID_NRCORES 0x0F000000
19 #define BCMA_CC_ID_TYPE 0xF0000000
21 #define BCMA_CC_CAP 0x0004 /* Capabilities */
22 #define BCMA_CC_CAP_NRUART 0x00000003 /* # of UARTs */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
[all …]
/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drx.h14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
27 * (REPLY_RX_PHY_CMD = 0xc0)
70 * bits 0:3 - reserved
78 CSUM_RXA_RESERVED_MASK = 0x000f,
79 CSUM_RXA_MICSIZE_MASK = 0x00f0,
80 CSUM_RXA_HEADERLEN_MASK = 0x1f00,
110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
[all …]
/linux/drivers/net/fddi/
H A Ddefxx.h70 #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */
75 #define PI_PHY_K_S 0 /* Index to S phy */
76 #define PI_PHY_K_A 0 /* Index to A phy */
95 #define PI_FMC_DESCR_V_LEN 0
97 #define PI_FMC_DESCR_M_SOP 0x80000000
98 #define PI_FMC_DESCR_M_EOP 0x40000000
99 #define PI_FMC_DESCR_M_FSC 0x38000000
100 #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000
101 #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000
102 #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000
[all …]
/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800.h49 #define RF2820 0x0001
50 #define RF2850 0x0002
51 #define RF2720 0x0003
52 #define RF2750 0x0004
53 #define RF3020 0x0005
54 #define RF2020 0x0006
55 #define RF3021 0x0007
56 #define RF3022 0x0008
57 #define RF3052 0x0009
58 #define RF2853 0x000a
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]

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