Searched +full:0 +full:x1fc0000 (Results 1 – 7 of 7) sorted by relevance
4 /memreserve/ 0x00000000 0x00001000; // reserved5 /memreserve/ 0x00001000 0x000ef000; // ROM data6 /memreserve/ 0x000f0000 0x004cc000; // reserved26 cpu@0 {33 reg = <0x0 0x08000000>;45 reg = <0x1b1c0000 0x20000>;61 reg = <0x1b200000 0x1000>;64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */71 reg = <0x1c000000 0x2000000>;81 user-fs@0 {[all …]
54 reg = <0x1fc0000 0x30000>;
54 reg = <0x0 0x40040000 0x0 0x1fc0000>;
23 #size-cells = <0>;25 cpu0: cpu@0 {28 reg = <0x0>;30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;31 i-cache-size = <0xc000>;34 d-cache-size = <0x8000>;45 reg = <0x1>;47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;48 i-cache-size = <0xc000>;51 d-cache-size = <0x8000>;[all …]
38 #clock-cells = <0>;46 #clock-cells = <0>;52 #size-cells = <0>;54 CPU0: cpu@0 {57 reg = <0x0 0x0>;58 clocks = <&cpufreq_hw 0>;61 qcom,freq-domain = <&cpufreq_hw 0>;81 reg = <0x0 0x100>;82 clocks = <&cpufreq_hw 0>;85 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
39 #clock-cells = <0>;45 #clock-cells = <0>;52 #size-cells = <0>;54 CPU0: cpu@0 {57 reg = <0x0 0x0>;62 qcom,freq-domain = <&cpufreq_hw 0>;64 clocks = <&cpufreq_hw 0>;81 reg = <0x0 0x100>;86 qcom,freq-domain = <&cpufreq_hw 0>;88 clocks = <&cpufreq_hw 0>;[all …]
80 #clock-cells = <0>;88 #clock-cells = <0>;94 #size-cells = <0>;96 CPU0: cpu@0 {99 reg = <0x0 0x0>;100 clocks = <&cpufreq_hw 0>;107 qcom,freq-domain = <&cpufreq_hw 0>;109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,115 cache-size = <0x20000>;121 cache-size = <0x400000>;[all …]