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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,milos-gcc.yaml26 - description: PCIE 0 Pipe clock source
28 - description: UFS Phy Rx symbol 0 clock source
30 - description: UFS Phy Tx symbol 0 clock source
48 reg = <0x00100000 0x1f4200>;
53 <&ufs_mem_phy 0>,
H A Dqcom,sar2130p-gcc.yaml26 - description: PCIe 0 pipe clock
53 reg = <0x100000 0x1f4200>;
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsm4450.dtsi29 #clock-cells = <0>;
35 #clock-cells = <0>;
39 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu0: cpu@0 {
54 reg = <0x0 0x0>;
55 clocks = <&cpufreq_hw 0>;
60 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
[all …]
H A Dqdu1000.dtsi28 #clock-cells = <0>;
34 #clock-cells = <0>;
40 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0x0 0x0>;
46 clocks = <&cpufreq_hw 0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
68 reg = <0x0 0x100>;
69 clocks = <&cpufreq_hw 0>;
73 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8750.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0x0 0x0>;
50 reg = <0x0 0x100>;
60 reg = <0x0 0x200>;
70 reg = <0x0 0x300>;
80 reg = <0x0 0x400>;
90 reg = <0x0 0x500>;
100 reg = <0x0 0x10000>;
116 reg = <0x0 0x10100>;
[all …]
H A Dsar2130p.dtsi34 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0x0 0x0>;
53 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
79 clocks = <&cpufreq_hw 0>;
82 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8450.dtsi40 #clock-cells = <0>;
46 #clock-cells = <0>;
53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0x0 0x0>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
65 clocks = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
87 qcom,freq-domain = <&cpufreq_hw 0>;
89 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi40 #clock-cells = <0>;
45 #clock-cells = <0>;
49 #clock-cells = <0>;
57 #clock-cells = <0>;
67 #size-cells = <0>;
69 cpu0: cpu@0 {
72 reg = <0 0>;
73 clocks = <&cpufreq_hw 0>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
98 reg = <0 0x100>;
[all …]
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
78 clocks = <&cpufreq_hw 0>;
88 qcom,freq-domain = <&cpufreq_hw 0>;
118 reg = <0 0x100>;
[all …]