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/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac-phy.c15 #define EMAC_MDIO_CTRL 0x001414
16 #define EMAC_PHY_STS 0x001418
17 #define EMAC_MDIO_EX_CTRL 0x001440
24 #define MDIO_CLK_SEL_BMSK 0x7000000
29 #define MDIO_REG_ADDR_BMSK 0x1f0000
31 #define MDIO_DATA_BMSK 0xffff
32 #define MDIO_DATA_SHFT 0
35 #define PHY_ADDR_BMSK 0x1f0000
38 #define MDIO_CLK_25_4 0
88 return 0; in emac_mdio_write()
[all …]
/linux/drivers/media/rc/
H A Dir-sony-decoder.c44 return 0; in ir_sony_decode()
62 data->count = 0; in ir_sony_decode()
64 return 0; in ir_sony_decode()
74 return 0; in ir_sony_decode()
88 return 0; in ir_sony_decode()
101 return 0; in ir_sony_decode()
119 device = bitrev8((data->bits << 3) & 0xF8); in ir_sony_decode()
120 subdevice = 0; in ir_sony_decode()
121 function = bitrev8((data->bits >> 4) & 0xFE); in ir_sony_decode()
128 device = bitrev8((data->bits >> 0) & 0xFF); in ir_sony_decode()
[all …]
H A Dir-rc5-decoder.c50 return 0; in ir_rc5_decode()
61 return 0; in ir_rc5_decode()
88 return 0; in ir_rc5_decode()
117 return 0; in ir_rc5_decode()
119 xdata = (data->bits & 0x0003F) >> 0; in ir_rc5_decode()
120 command = (data->bits & 0x00FC0) >> 6; in ir_rc5_decode()
121 system = (data->bits & 0x1F000) >> 12; in ir_rc5_decode()
122 toggle = (data->bits & 0x20000) ? 1 : 0; in ir_rc5_decode()
123 command += (data->bits & 0x40000) ? 0 : 0x40; in ir_rc5_decode()
132 return 0; in ir_rc5_decode()
[all …]
/linux/Documentation/i2c/
H A Di2c-stub.rst26 explicitly by setting the respective bits (0x03000000) in the functionality
52 value 0x1f0000 would only enable the quick, byte and byte data
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
H A Dgoya_masks.h180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_3_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_3_0_1_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-kontron-sl.dtsi19 reg = <0x0 0x40000000 0 0x80000000>;
61 pinctrl-0 = <&pinctrl_ecspi1>;
65 flash@0 {
68 reg = <0>;
75 partition@0 {
77 reg = <0x0 0x1e0000>;
82 reg = <0x1e0000 0x10000>;
87 reg = <0x1f0000 0x10000>;
96 pinctrl-0 = <&pinctrl_i2c1>;
101 reg = <0x25>;
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_edma0_core_masks.h24 #define DCORE0_EDMA0_CORE_CFG_0_EN_SHIFT 0
25 #define DCORE0_EDMA0_CORE_CFG_0_EN_MASK 0x1
28 #define DCORE0_EDMA0_CORE_CFG_1_HALT_SHIFT 0
29 #define DCORE0_EDMA0_CORE_CFG_1_HALT_MASK 0x1
31 #define DCORE0_EDMA0_CORE_CFG_1_FLUSH_MASK 0x2
34 #define DCORE0_EDMA0_CORE_PROT_VAL_SHIFT 0
35 #define DCORE0_EDMA0_CORE_PROT_VAL_MASK 0x1
37 #define DCORE0_EDMA0_CORE_PROT_ERR_VAL_MASK 0x2
40 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
41 #define DCORE0_EDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
[all …]
H A Darc_farm_kdma_masks.h24 #define ARC_FARM_KDMA_CFG_0_EN_SHIFT 0
25 #define ARC_FARM_KDMA_CFG_0_EN_MASK 0x1
28 #define ARC_FARM_KDMA_CFG_1_HALT_SHIFT 0
29 #define ARC_FARM_KDMA_CFG_1_HALT_MASK 0x1
31 #define ARC_FARM_KDMA_CFG_1_FLUSH_MASK 0x2
34 #define ARC_FARM_KDMA_PROT_VAL_SHIFT 0
35 #define ARC_FARM_KDMA_PROT_VAL_MASK 0x1
37 #define ARC_FARM_KDMA_PROT_ERR_VAL_MASK 0x2
40 #define ARC_FARM_KDMA_CKG_HBW_RBUF_SHIFT 0
41 #define ARC_FARM_KDMA_CKG_HBW_RBUF_MASK 0x1
[all …]
H A Dpdma0_core_masks.h24 #define PDMA0_CORE_CFG_0_EN_SHIFT 0
25 #define PDMA0_CORE_CFG_0_EN_MASK 0x1
28 #define PDMA0_CORE_CFG_1_HALT_SHIFT 0
29 #define PDMA0_CORE_CFG_1_HALT_MASK 0x1
31 #define PDMA0_CORE_CFG_1_FLUSH_MASK 0x2
34 #define PDMA0_CORE_PROT_VAL_SHIFT 0
35 #define PDMA0_CORE_PROT_VAL_MASK 0x1
37 #define PDMA0_CORE_PROT_ERR_VAL_MASK 0x2
40 #define PDMA0_CORE_CKG_HBW_RBUF_SHIFT 0
41 #define PDMA0_CORE_CKG_HBW_RBUF_MASK 0x1
[all …]
/linux/sound/soc/codecs/
H A Djz4740.c23 #define JZ4740_REG_CODEC_1 0x0
24 #define JZ4740_REG_CODEC_2 0x4
44 #define JZ4740_CODEC_1_RESET BIT(0)
55 #define JZ4740_CODEC_2_INPUT_VOLUME_MASK 0x1f0000
56 #define JZ4740_CODEC_2_SAMPLE_RATE_MASK 0x000f00
57 #define JZ4740_CODEC_2_MIC_BOOST_GAIN_MASK 0x000030
58 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_MASK 0x000003
63 #define JZ4740_CODEC_2_HEADPHONE_VOLUME_OFFSET 0
66 { JZ4740_REG_CODEC_1, 0x021b2302 },
67 { JZ4740_REG_CODEC_2, 0x00170803 },
[all …]
/linux/drivers/net/ethernet/moxa/
H A Dmoxart_ether.h18 #define TX_REG_OFFSET_DESC0 0
23 #define RX_REG_OFFSET_DESC0 0
28 #define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
29 #define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
30 #define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
31 #define TX_DESC1_BUF_SIZE_MASK 0x7ff
32 #define TX_DESC1_LTS 0x8000000 /* last TX packet */
33 #define TX_DESC1_FTS 0x10000000 /* first TX packet */
34 #define TX_DESC1_FIFO_COMPLETE 0x20000000
35 #define TX_DESC1_INTR_COMPLETE 0x40000000
[all …]
/linux/drivers/net/ethernet/renesas/
H A Dsh_eth.h29 EDSR = 0,
127 /* TSU_ADR{H,L}{0..31} are assumed to be contiguous */
164 EDSR_ENT = 0x01, EDSR_ENR = 0x02,
170 GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
175 EDMR_NBST = 0x80,
176 EDMR_EL = 0x40, /* Litte endian */
177 EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
178 EDMR_SRST_GETHER = 0x03,
179 EDMR_SRST_ETHER = 0x01,
184 EDTRR_TRNS_GETHER = 0x03,
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs-plat.c25 #define DW_VR_CSR_VIEWPORT 0xff
38 return FIELD_PREP(0x1f0000, dev) | FIELD_PREP(0xffff, reg); in xpcs_mmio_addr_format()
43 return FIELD_GET(0x1fff00, csr); in xpcs_mmio_addr_page()
48 return FIELD_GET(0xff, csr); in xpcs_mmio_addr_offset()
69 ret = readl(pxpcs->reg_base + (ofs << 2)) & 0xffff; in xpcs_mmio_read_reg_indirect()
110 return 0; in xpcs_mmio_write_reg_indirect()
127 ret = readl(pxpcs->reg_base + (csr << 2)) & 0xffff; in xpcs_mmio_read_reg_direct()
162 return 0; in xpcs_mmio_write_reg_direct()
169 if (addr != 0) in xpcs_mmio_read_c22()
182 if (addr != 0) in xpcs_mmio_write_c22()
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dvexpress-v2m-rs1.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #clock-cells = <0>;
57 gpios = <&v2m_led_gpios 0 0>;
63 gpios = <&v2m_led_gpios 1 0>;
69 gpios = <&v2m_led_gpios 2 0>;
75 gpios = <&v2m_led_gpios 3 0>;
81 gpios = <&v2m_led_gpios 4 0>;
87 gpios = <&v2m_led_gpios 5 0>;
93 gpios = <&v2m_led_gpios 6 0>;
[all …]
/linux/drivers/media/common/saa7146/
H A Dsaa7146_vbi.c13 int count = 0; in vbi_workaround()
34 saa7146_write(dev, BASE_PAGE3, 0x0); in vbi_workaround()
35 saa7146_write(dev, NUM_LINE_BYTE3, (2<<16)|((vbi_pixel_to_capture)<<0)); in vbi_workaround()
41 WRITE_RPS1(0xc000008c); in vbi_workaround()
43 if ( 0 != (SAA7146_USE_PORT_B_FOR_VBI & dev->ext_vv_data->flags)) { in vbi_workaround()
86 for(i = 0; i < 2; i++) { in vbi_workaround()
91 saa7146_write(dev, NUM_LINE_BYTE3, (1<<16)|(2<<0)); in vbi_workaround()
120 DEB_VBI("aborted (rps:0x%08x)\n", in vbi_workaround()
132 return 0; in vbi_workaround()
141 int count = 0; in saa7146_set_vbi_capture()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_8_0_sh_mask.h27 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON_MASK 0x1
28 #define PIPE0_PG_CONFIG__PIPE0_POWER_FORCEON__SHIFT 0x0
29 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE_MASK 0x1
30 #define PIPE0_PG_ENABLE__PIPE0_POWER_GATE__SHIFT 0x0
31 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA_MASK 0xffffff
32 #define PIPE0_PG_STATUS__PIPE0_PGFSM_READ_DATA__SHIFT 0x0
33 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS_MASK 0x3000000
34 #define PIPE0_PG_STATUS__PIPE0_DEBUG_PWR_STATUS__SHIFT 0x18
35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000
36 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE__SHIFT 0x1c
[all …]

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