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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,gcc-qcm2290.yaml48 reg = <0x01400000 0x1f0000>;
H A Dqcom,gcc-sdx55.yaml49 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sm6115.yaml48 reg = <0x01400000 0x1f0000>;
H A Dqcom,gcc-sm6125.yaml48 reg = <0x01400000 0x1f0000>;
H A Dqcom,gcc-sm8150.yaml49 reg = <0x00100000 0x1f0000>;
H A Dqcom,sm6375-gcc.yaml43 reg = <0x01400000 0x1f0000>;
H A Dqcom,gcc-sm8250.yaml51 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sm6350.yaml50 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sc8180x.yaml56 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sc7180.yaml57 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sc7280.yaml27 - description: PCIE-0 pipe clock source
29 - description: USF phy rx symbol 0 clock source
31 - description: USF phy tx symbol 0 clock source
68 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sdm845.yaml72 - description: PCIE 0 Pipe clock source
90 reg = <0x100000 0x1f0000>;
H A Dqcom,gcc-sm8350.yaml26 - description: PCIE 0 Pipe clock source (Optional clock)
28 - description: UFS card Rx symbol 0 clock source (Optional clock)
30 - description: UFS card Tx symbol 0 clock source (Optional clock)
31 - description: UFS phy Rx symbol 0 clock source (Optional clock)
33 - description: UFS phy Tx symbol 0 clock source (Optional clock)
70 reg = <0x00100000 0x1f0000>;
H A Dqcom,gcc-sc8280xp.yaml82 reg = <0x00100000 0x1f0000>;
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-kontron-sl.dtsi19 reg = <0x0 0x40000000 0 0x80000000>;
61 pinctrl-0 = <&pinctrl_ecspi1>;
65 flash@0 {
68 reg = <0>;
75 partition@0 {
77 reg = <0x0 0x1e0000>;
82 reg = <0x1e0000 0x10000>;
87 reg = <0x1f0000 0x10000>;
96 pinctrl-0 = <&pinctrl_i2c1>;
101 reg = <0x25>;
[all …]
H A Dimx8mm-kontron-osm-s.dtsi26 reg = <0x0 0x40000000 0 0x80000000>;
36 pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
59 pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
70 pinctrl-0 = <&pinctrl_reg_usb2_vbus>;
81 pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>;
92 pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>;
135 pinctrl-0 = <&pinctrl_ecspi1>;
139 flash@0 {
142 reg = <0>;
149 partition@0 {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Drtsm_ve-motherboard.dtsi13 #clock-cells = <0>;
20 #clock-cells = <0>;
27 #clock-cells = <0>;
49 #clock-cells = <0>;
55 arm,vexpress-sysreg,func = <5 0>;
60 arm,vexpress-sysreg,func = <7 0>;
65 arm,vexpress-sysreg,func = <8 0>;
70 arm,vexpress-sysreg,func = <9 0>;
75 arm,vexpress-sysreg,func = <11 0>;
83 ranges = <0 0x8000000 0 0x8000000 0x18000000>;
[all …]
H A Dvexpress-v2m-rs1.dtsi23 v2m_fixed_3v3: fixed-regulator-0 {
33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #clock-cells = <0>;
57 gpios = <&v2m_led_gpios 0 0>;
63 gpios = <&v2m_led_gpios 1 0>;
69 gpios = <&v2m_led_gpios 2 0>;
75 gpios = <&v2m_led_gpios 3 0>;
81 gpios = <&v2m_led_gpios 4 0>;
87 gpios = <&v2m_led_gpios 5 0>;
[all …]
/freebsd/sys/dev/ae/
H A Dif_aereg.h31 #define AE_MASTER_REG 0x1400
33 #define AE_MASTER_SOFT_RESET 0x1 /* Reset adapter. */
34 #define AE_MASTER_MTIMER_EN 0x2 /* Unknown. */
35 #define AE_MASTER_IMT_EN 0x4 /* Interrupt moderation timer enable. */
36 #define AE_MASTER_MANUAL_INT 0x8 /* Software manual interrupt. */
38 #define AE_MASTER_REVNUM_MASK 0xff
40 #define AE_MASTER_DEVID_MASK 0xff
45 #define AE_ISR_REG 0x1600
46 #define AE_ISR_TIMER 0x00000001 /* Counter expired. */
47 #define AE_ISR_MANUAL 0x00000002 /* Manual interrupt occuried. */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2m-rs1.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
47 #clock-cells = <0>;
57 gpios = <&v2m_led_gpios 0 0>;
63 gpios = <&v2m_led_gpios 1 0>;
69 gpios = <&v2m_led_gpios 2 0>;
75 gpios = <&v2m_led_gpios 3 0>;
81 gpios = <&v2m_led_gpios 4 0>;
87 gpios = <&v2m_led_gpios 5 0>;
93 gpios = <&v2m_led_gpios 6 0>;
[all …]
/freebsd/sys/contrib/dev/mediatek/mt76/mt7925/
H A Dpci.c14 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
57 dev->backup_l1 = 0; in mt7925_reg_remap_restore()
62 dev->backup_l2 = 0; in mt7925_reg_remap_restore()
103 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */ in __mt7925_reg_addr()
104 { 0x54000000, 0x002000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA0 */ in __mt7925_reg_addr()
105 { 0x55000000, 0x003000, 0x0001000 }, /* WFDMA PCIE0 MCU DMA1 */ in __mt7925_reg_addr()
106 { 0x56000000, 0x004000, 0x0001000 }, /* WFDMA reserved */ in __mt7925_reg_addr()
107 { 0x57000000, 0x005000, 0x0001000 }, /* WFDMA MCU wrap CR */ in __mt7925_reg_addr()
108 { 0x58000000, 0x006000, 0x0001000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ in __mt7925_reg_addr()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-sdx55.dtsi20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
/freebsd/contrib/tcpdump/
H A Dprint-udp.c105 if ((ts & 0xf060) != 0) { in vat_print()
109 ts & 0x3ff, ts >> 10); in vat_print()
118 i0 = GET_BE_U_4(&((const u_int *)hdr)[0]); in vat_print()
122 i0 & 0xffff, in vat_print()
123 i1, i0 & 0x800000? "*" : ""); in vat_print()
125 if (i0 & 0x1f0000) in vat_print()
126 ND_PRINT(" f%u", (i0 >> 16) & 0x1f); in vat_print()
127 if (i0 & 0x3f000000) in vat_print()
128 ND_PRINT(" s%u", (i0 >> 24) & 0x3f); in vat_print()
146 i0 = GET_BE_U_4(&((const u_int *)hdr)[0]); in rtp_print()
[all …]

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