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/linux/Documentation/devicetree/bindings/nvmem/
H A Dqcom,qfprom.yaml98 reg = <0 0x00784000 0 0x8ff>,
99 <0 0x00780000 0 0x7a0>,
100 <0 0x00782000 0 0x100>,
101 <0 0x00786000 0 0x1fff>;
110 reg = <0x25b 0x1>;
123 reg = <0 0x00784000 0 0x8ff>;
128 reg = <0x1eb 0x1>;
/linux/arch/x86/include/uapi/asm/
H A Dbootparam.h8 #define RAMDISK_IMAGE_START_MASK 0x07FF
9 #define RAMDISK_PROMPT_FLAG 0x8000
10 #define RAMDISK_LOAD_FLAG 0x4000
13 #define LOADED_HIGH (1<<0)
20 #define XLF_KERNEL_64 (1<<0)
117 struct screen_info screen_info; /* 0x000 */
118 struct apm_bios_info apm_bios_info; /* 0x040 */
119 __u8 _pad2[4]; /* 0x054 */
120 __u64 tboot_addr; /* 0x058 */
121 struct ist_info ist_info; /* 0x060 */
[all …]
/linux/drivers/mfd/
H A Drz-mtu3.c28 /******* MTU3 registers (original offset is +0x1200) *******/
30 [RZ_MTU3_CHAN_0] = MTU_8BIT_CH_0(0x104, 0x090, 0x100, 0x128, 0x101, 0x102, 0x103, 0x126),
31 [RZ_MTU3_CHAN_1] = MTU_8BIT_CH_1_2(0x184, 0x091, 0x185, 0x180, 0x194, 0x181, 0x182),
32 [RZ_MTU3_CHAN_2] = MTU_8BIT_CH_1_2(0x204, 0x092, 0x205, 0x200, 0x20c, 0x201, 0x202),
33 …[RZ_MTU3_CHAN_3] = MTU_8BIT_CH_3_4_6_7(0x008, 0x093, 0x02c, 0x000, 0x04c, 0x002, 0x004, 0x005, 0x0…
34 …[RZ_MTU3_CHAN_4] = MTU_8BIT_CH_3_4_6_7(0x009, 0x094, 0x02d, 0x001, 0x04d, 0x003, 0x006, 0x007, 0x0…
35 …[RZ_MTU3_CHAN_5] = MTU_8BIT_CH_5(0xab2, 0x1eb, 0xab4, 0xab6, 0xa84, 0xa85, 0xa86, 0xa94, 0xa95, 0x…
36 …[RZ_MTU3_CHAN_6] = MTU_8BIT_CH_3_4_6_7(0x808, 0x893, 0x82c, 0x800, 0x84c, 0x802, 0x804, 0x805, 0x8…
37 …[RZ_MTU3_CHAN_7] = MTU_8BIT_CH_3_4_6_7(0x809, 0x894, 0x82d, 0x801, 0x84d, 0x803, 0x806, 0x807, 0x8…
38 [RZ_MTU3_CHAN_8] = MTU_8BIT_CH_8(0x404, 0x098, 0x400, 0x406, 0x401, 0x402, 0x403)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_d.h27 #define ixTHM_TCON_CSR_CONFIG 0xd82014a4
28 #define ixTHM_TCON_CSR_DATA 0xd82014a8
29 #define ixTHM_TCON_HTC 0xd8200c64
30 #define ixTHM_TCON_CUR_TMP 0xd8200ca4
31 #define ixTHM_TCON_THERM_TRIP 0xd8200ce4
32 #define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00
33 #define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04
34 #define ixTHM_THERMAL_INT_ENA 0xd8200d10
35 #define ixTHM_THERMAL_INT_CTRL 0xd8200d14
36 #define ixTHM_THERMAL_INT_STATUS 0xd8200d18
[all …]
/linux/Documentation/mm/
H A Dslub.rst107 If the file contains 1, the option is enabled, 0 means disabled. The debug
117 failslab file is writable, so writing 1 or 0 will enable or disable
154 .. slab_min_order=x (default 0)
174 ``debug_guardpage_minorder=N`` (N > 0), forces setting
175 ``slab_max_order`` to 0, what cause minimum possible order of
196 INFO: 0xc90f6d28-0xc90f6d2b. First byte 0x00 instead of 0xcc
197 INFO: Slab 0xc528c530 flags=0x400000c3 inuse=61 fp=0xc90f6d58
198 INFO: Object 0xc90f6d20 @offset=3360 fp=0xc90f6d58
199 INFO: Allocated in get_modalias+0x61/0xf5 age=53 cpu=1 pid=554
201 Bytes b4 (0xc90f6d10): 00 00 00 00 00 00 00 00 5a 5a 5a 5a 5a 5a 5a 5a ........ZZZZZZZZ
[all …]
/linux/drivers/gpu/drm/amd/include/
H A Dv11_structs.h28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t gds_bkup_base_lo; // offset: 2 (0x2)
31 uint32_t gds_bkup_base_hi; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
H A Dv12_structs.h28 uint32_t shadow_base_lo; // offset: 0 (0x0)
29 uint32_t shadow_base_hi; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t fw_work_area_base_lo; // offset: 4 (0x4)
33 uint32_t fw_work_area_base_hi; // offset: 5 (0x5)
34 uint32_t shadow_initialized; // offset: 6 (0x6)
35 uint32_t ib_vmid; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
H A Dv10_structs.h28 uint32_t reserved_0; // offset: 0 (0x0)
29 uint32_t reserved_1; // offset: 1 (0x1)
30 uint32_t reserved_2; // offset: 2 (0x2)
31 uint32_t reserved_3; // offset: 3 (0x3)
32 uint32_t reserved_4; // offset: 4 (0x4)
33 uint32_t reserved_5; // offset: 5 (0x5)
34 uint32_t reserved_6; // offset: 6 (0x6)
35 uint32_t reserved_7; // offset: 7 (0x7)
36 uint32_t reserved_8; // offset: 8 (0x8)
37 uint32_t reserved_9; // offset: 9 (0x9)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_PERF_CID 0x9c6
36 #define mmMC_ARB_GECC2 0x9c9
[all …]
H A Dgmc_8_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
[all …]
/linux/sound/drivers/opl4/
H A Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_n.h11 #define B43_NPHY_BBCFG B43_PHY_N(0x001) /* BB config */
12 #define B43_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
13 #define B43_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
14 #define B43_NPHY_CHANNEL B43_PHY_N(0x005) /* Channel */
15 #define B43_NPHY_TXERR B43_PHY_N(0x007) /* TX error */
16 #define B43_NPHY_BANDCTL B43_PHY_N(0x009) /* Band control */
17 #define B43_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_enum.h28 NUMBER_UNORM = 0x0,
29 NUMBER_SNORM = 0x1,
30 NUMBER_USCALED = 0x2,
31 NUMBER_SSCALED = 0x3,
32 NUMBER_UINT = 0x4,
33 NUMBER_SINT = 0x5,
34 NUMBER_SRGB = 0x6,
35 NUMBER_FLOAT = 0x7,
38 SWAP_STD = 0x0,
39 SWAP_ALT = 0x1,
[all …]
H A Dgfx_8_1_enum.h28 NUMBER_UNORM = 0x0,
29 NUMBER_SNORM = 0x1,
30 NUMBER_USCALED = 0x2,
31 NUMBER_SSCALED = 0x3,
32 NUMBER_UINT = 0x4,
33 NUMBER_SINT = 0x5,
34 NUMBER_SRGB = 0x6,
35 NUMBER_FLOAT = 0x7,
38 SWAP_STD = 0x0,
39 SWAP_ALT = 0x1,
[all …]