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12

/linux/drivers/media/pci/bt8xx/
H A Dbttv-audio-hook.c30 for (loops = 17; loops >= 0 ; loops--) { in winview_volume()
70 gpio_inout(0x300, 0x300); in gvbctv3pci_audio()
74 con = 0x000; in gvbctv3pci_audio()
77 con = 0x300; in gvbctv3pci_audio()
80 con = 0x200; in gvbctv3pci_audio()
83 gpio_bits(0x300, con); in gvbctv3pci_audio()
97 con = 0x300; in gvbctv5pci_audio()
100 con = 0x100; in gvbctv5pci_audio()
103 con = 0x000; in gvbctv5pci_audio()
106 if (con != (val & 0x300)) { in gvbctv5pci_audio()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-kontron-sl.dtsi19 reg = <0x0 0x40000000 0 0x80000000>;
61 pinctrl-0 = <&pinctrl_ecspi1>;
65 flash@0 {
68 reg = <0>;
75 partition@0 {
77 reg = <0x0 0x1e0000>;
82 reg = <0x1e0000 0x10000>;
87 reg = <0x1f0000 0x10000>;
96 pinctrl-0 = <&pinctrl_i2c1>;
101 reg = <0x25>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-linksys-rango.dts20 wan_amber@0 {
22 reg = <0x0>;
27 reg = <0x1>;
32 reg = <0x5>;
37 reg = <0x6>;
42 reg = <0x7>;
47 reg = <0x8>;
52 reg = <0x9>;
89 partition@0 {
91 reg = <0x0000000 0x200000>; /* 2MiB */
[all …]
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-afe-common.h121 MT8365_AFE_APLL1 = 0,
127 MT8365_AFE_1ST_I2S = 0,
133 MT8365_AFE_I2S_SEPARATE_CLOCK = 0,
138 MT8365_AFE_TDM_OUT_I2S = 0,
144 AFE_TDM_CH_START_O28_O29 = 0,
152 MT8365_PCM_FORMAT_I2S = 0,
159 MT8365_FS_8K = 0,
177 FS_8000HZ = 0, /* 0000b */
205 MT8365_AFE_IRQ_DIR_MCU = 0,
212 MT8365_I2S0_MCK = 0,
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-tao3530.dtsi25 cpu@0 {
32 reg = <0x80000000 0x10000000>; /* 256 MB */
50 #phy-cells = <0>;
75 OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
76 OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
77 OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
78 OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
79 OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
80 OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
81 OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
[all …]
H A Domap3-beagle.dts14 cpu@0 {
21 reg = <0x80000000 0x10000000>; /* 256 MB */
64 #phy-cells = <0>;
80 linux,code = <0x114>;
91 pinctrl-0 = <&tfp410_pins>;
95 #size-cells = <0>;
97 port@0 {
98 reg = <0>;
143 reg = <0x5401b000 0x1000>;
158 reg = <0x54010000 0x1000>;
[all …]
H A Domap3-lilly-a83x.dtsi13 bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0";
18 reg = <0x80000000 0x8000000>; /* 128 MB */
50 #phy-cells = <0>;
59 OMAP3_WKUP_IOPAD(0x2a5a, PIN_INPUT | MUX_MODE4) /* reserved.gpio_129 */
65 OMAP3_WKUP_IOPAD(0x2a16, PIN_INPUT_PULLUP | MUX_MODE4) /* sys_boot6.gpio_8 */
71 OMAP3_WKUP_IOPAD(0x2a56, PIN_INPUT | MUX_MODE4) /* reserved.gpio_126 */
81 OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */
82 OMAP3_CORE1_IOPAD(0x217e, PIN_OUTPUT | MUX_MODE0) /* uart1_rts.uart1_rts */
83 OMAP3_CORE1_IOPAD(0x2180, PIN_INPUT | MUX_MODE0) /* uart1_cts.uart1_cts */
84 OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
[all …]
H A Domap3-pandora-common.dtsi13 cpu@0 {
20 reg = <0x80000000 0x20000000>; /* 512 MB */
29 #clock-cells = <0>;
50 pinctrl-0 = <&led_pins>;
54 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */
85 pinctrl-0 = <&button_pins>;
104 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; /* GPIO_96 */
201 linux,code = <0x00>; /* SW_LID lid shut */
202 linux,input-type = <0x05>; /* EV_SW */
212 #phy-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sx-nitrogen6sx.dts16 reg = <0x80000000 0x40000000>;
21 pwms = <&pwm4 0 5000000 0>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
61 pinctrl-0 = <&pinctrl_usbotg1_vbus>;
72 pinctrl-0 = <&pinctrl_reg_wlan>;
99 pinctrl-0 = <&pinctrl_audmux>;
106 pinctrl-0 = <&pinctrl_ecspi1>;
109 flash: flash@0 {
112 reg = <0>;
116 partition@0 {
[all …]
/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dmme3_ctrl_regs.h22 #define mmMME3_CTRL_ARCH_STATUS 0x1E0000
24 #define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_S 0x1E0008
26 #define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_L 0x1E000C
28 #define mmMME3_CTRL_ARCH_BASE_ADDR_HIGH_O 0x1E0010
30 #define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_S 0x1E0014
32 #define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_L 0x1E0018
34 #define mmMME3_CTRL_ARCH_BASE_ADDR_LOW_O 0x1E001C
36 #define mmMME3_CTRL_ARCH_HEADER_LOW 0x1E0020
38 #define mmMME3_CTRL_ARCH_HEADER_HIGH 0x1E0024
40 #define mmMME3_CTRL_ARCH_CONV_KERNEL_SIZE_MINUS_1 0x1E0028
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/smu/
H A Dsmu_8_0_sh_mask.h27 #define THM_TCON_CSR_CONFIG__TCC_ADDR_MASK 0x3ff
28 #define THM_TCON_CSR_CONFIG__TCC_ADDR__SHIFT 0x0
29 #define THM_TCON_CSR_CONFIG__TCC_READ_OP_MASK 0x400
30 #define THM_TCON_CSR_CONFIG__TCC_READ_OP__SHIFT 0xa
31 #define THM_TCON_CSR_DATA__TCC_DATA_MASK 0xfff
32 #define THM_TCON_CSR_DATA__TCC_DATA__SHIFT 0x0
33 #define THM_TCON_CSR_DATA__TCC_REQ_DONE_MASK 0x1000
34 #define THM_TCON_CSR_DATA__TCC_REQ_DONE__SHIFT 0xc
35 #define THM_TCON_HTC__HTC_EN_MASK 0x1
36 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0
[all …]
H A Dsmu_7_0_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_1_0_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
H A Dsmu_7_0_1_sh_mask.h27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-dai-src.c18 0x0dbae6, 0xff9b0a, 0x0dbae6, 0x05e488, 0xe072b9, 0x000002,
19 0x0dbae6, 0x000f3b, 0x0dbae6, 0x06a537, 0xe17d79, 0x000002,
20 0x0dbae6, 0x01246a, 0x0dbae6, 0x087261, 0xe306be, 0x000002,
21 0x0dbae6, 0x03437d, 0x0dbae6, 0x0bc16f, 0xe57c87, 0x000002,
22 0x0dbae6, 0x072981, 0x0dbae6, 0x111dd3, 0xe94f2a, 0x000002,
23 0x0dbae6, 0x0dc4a6, 0x0dbae6, 0x188611, 0xee85a0, 0x000002,
24 0x0dbae6, 0x168b9a, 0x0dbae6, 0x200e8f, 0xf3ccf1, 0x000002,
25 0x000000, 0x1b75cb, 0x1b75cb, 0x2374a2, 0x000000, 0x000001
29 0x09ae28, 0xf7d97d, 0x09ae28, 0x212a3d, 0xe0ac3a, 0x000002,
30 0x09ae28, 0xf8525a, 0x09ae28, 0x216d72, 0xe234be, 0x000002,
[all …]
H A Dmt8186-dai-i2s.c17 I2S_FMT_EIAJ = 0,
22 I2S_WLEN_16_BIT = 0,
27 I2S_HD_NORMAL = 0,
32 I2S1_SEL_O28_O29 = 0,
37 I2S_IN_PAD_CONNSYS = 0,
79 if (strncmp(name, "I2S0", 4) == 0) in get_i2s_id_by_name()
81 else if (strncmp(name, "I2S1", 4) == 0) in get_i2s_id_by_name()
83 else if (strncmp(name, "I2S2", 4) == 0) in get_i2s_id_by_name()
85 else if (strncmp(name, "I2S3", 4) == 0) in get_i2s_id_by_name()
97 if (dai_id < 0) in get_i2s_priv_by_name()
[all …]
/linux/arch/powerpc/include/asm/
H A Dreg_booke.h23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
48 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
49 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
50 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
56 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
[all …]
/linux/sound/soc/codecs/
H A Dcs47l35.c41 { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x140000 },
55 { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56 { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
[all …]
H A Dcs47l85.c41 { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x140000 },
55 { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56 { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
[all …]
H A Dcs47l90.c41 { .type = WMFW_ADSP2_PM, .base = 0x080000 },
42 { .type = WMFW_ADSP2_ZM, .base = 0x0e0000 },
43 { .type = WMFW_ADSP2_XM, .base = 0x0a0000 },
44 { .type = WMFW_ADSP2_YM, .base = 0x0c0000 },
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x160000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x120000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x140000 },
55 { .type = WMFW_ADSP2_PM, .base = 0x180000 },
56 { .type = WMFW_ADSP2_ZM, .base = 0x1e0000 },
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_3_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
H A Doss_3_0_1_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/linux/drivers/mfd/
H A Dcs47l35-tables.c18 { 0x460, 0x0c40 },
19 { 0x461, 0xcd1a },
20 { 0x462, 0x0c40 },
21 { 0x463, 0xb53b },
22 { 0x464, 0x0c40 },
23 { 0x465, 0x7503 },
24 { 0x466, 0x0c40 },
25 { 0x467, 0x4a41 },
26 { 0x468, 0x0041 },
27 { 0x469, 0x3491 },
[all …]

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