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/linux/include/linux/mfd/mt6359p/
H A Dregisters.h9 #define MT6359P_CHIP_VER 0x5930
12 #define MT6359P_HWCID 0x8
13 #define MT6359P_TOP_TRAP 0x50
14 #define MT6359P_TOP_TMA_KEY 0x3a8
15 #define MT6359P_BUCK_VCORE_ELR_NUM 0x152a
16 #define MT6359P_BUCK_VCORE_ELR0 0x152c
17 #define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa
18 #define MT6359P_BUCK_VGPU11_ELR0 0x15b4
19 #define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44
20 #define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46
[all …]
/linux/drivers/scsi/isci/
H A Dinit.c68 #define DRV_VERSION "1.2.0"
75 { PCI_VDEVICE(INTEL, 0x1D61),},
76 { PCI_VDEVICE(INTEL, 0x1D63),},
77 { PCI_VDEVICE(INTEL, 0x1D65),},
78 { PCI_VDEVICE(INTEL, 0x1D67),},
79 { PCI_VDEVICE(INTEL, 0x1D69),},
80 { PCI_VDEVICE(INTEL, 0x1D6B),},
81 { PCI_VDEVICE(INTEL, 0x1D60),},
82 { PCI_VDEVICE(INTEL, 0x1D62),},
83 { PCI_VDEVICE(INTEL, 0x1D64),},
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-msm8994.c33 .offset = 0,
36 .enable_reg = 0x1480,
37 .enable_mask = BIT(0),
50 .offset = 0,
63 .offset = 0x1dc0,
66 .enable_reg = 0x1480,
80 .offset = 0x1dc0,
94 { P_XO, 0 },
104 { P_XO, 0 },
116 F(50000000, P_GPLL0, 12, 0, 0),
[all …]
H A Dgcc-apq8084.c39 .l_reg = 0x0004,
40 .m_reg = 0x0008,
41 .n_reg = 0x000c,
42 .config_reg = 0x0014,
43 .mode_reg = 0x0000,
44 .status_reg = 0x001c,
57 .enable_reg = 0x1480,
58 .enable_mask = BIT(0),
70 .l_reg = 0x0044,
71 .m_reg = 0x0048,
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-usbdp.c29 #define UDPHY_PCS 0x4000
30 #define UDPHY_PMA 0x8000
38 #define DP_LANE_SEL_ALL GENMASK(7, 0)
41 #define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */
45 #define CMN_DP_LANE_EN_ALL GENMASK(3, 0)
47 #define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */
51 #define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */
53 #define CMN_LCPLL_SSC_EN BIT(0)
55 #define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */
59 #define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
[all …]
H A Ddcn_2_0_0_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]
/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822c_table.c16 0x83000000, 0x00000000, 0x40000000, 0x00000000,
17 0x1D90, 0x300001FF,
18 0x1D90, 0x300101FE,
19 0x1D90, 0x300201FD,
20 0x1D90, 0x300301FC,
21 0x1D90, 0x300401FB,
22 0x1D90, 0x300501FA,
23 0x1D90, 0x300601F9,
24 0x1D90, 0x300701F8,
25 0x1D90, 0x300801F7,
[all …]