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/linux/drivers/gpu/drm/amd/include/asic_reg/umc/
H A Dumc_6_7_0_sh_mask.h29 …C_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0
30 …_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10
31 …_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16
32 …_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18
33 …_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e
34 …_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20
35 …_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26
36 …_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28
37 …_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29
38 …_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b
[all …]
/linux/lib/raid6/
H A Dloongarch_simd.c16 * The vector algorithms are currently priority 0, which means the generic
52 for (d = 0; d < bytes; d += NSIZE*4) { in raid6_lsx_gen_syndrome()
54 asm volatile("vld $vr0, %0" : : "m"(dptr[z0][d+0*NSIZE])); in raid6_lsx_gen_syndrome()
55 asm volatile("vld $vr1, %0" : : "m"(dptr[z0][d+1*NSIZE])); in raid6_lsx_gen_syndrome()
56 asm volatile("vld $vr2, %0" : : "m"(dptr[z0][d+2*NSIZE])); in raid6_lsx_gen_syndrome()
57 asm volatile("vld $vr3, %0" : : "m"(dptr[z0][d+3*NSIZE])); in raid6_lsx_gen_syndrome()
58 asm volatile("vori.b $vr4, $vr0, 0"); in raid6_lsx_gen_syndrome()
59 asm volatile("vori.b $vr5, $vr1, 0"); in raid6_lsx_gen_syndrome()
60 asm volatile("vori.b $vr6, $vr2, 0"); in raid6_lsx_gen_syndrome()
61 asm volatile("vori.b $vr7, $vr3, 0"); in raid6_lsx_gen_syndrome()
[all …]
H A Dneon.uc44 * The MASK() operation returns 0xFF in any byte for which the high
45 * bit is 1, 0x00 for any byte for which the high bit is 0.
64 const unative_t x1d = vdupq_n_u8(0x1d);
70 for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
72 for ( z = z0-1 ; z >= 0 ; z-- ) {
78 w2$$ = vandq_u8(w2$$, x1d);
95 const unative_t x1d = vdupq_n_u8(0x1d);
101 for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
112 w2$$ = vandq_u8(w2$$, x1d);
121 w2$$ = PMUL(w2$$, x1d);
[all …]
/linux/crypto/
H A Ddh.c27 memset(ctx, 0, sizeof(*ctx)); in dh_clear_ctx()
50 return (p_len < 2048) ? -EINVAL : 0; in dh_check_params_length()
52 return (p_len < 1536) ? -EINVAL : 0; in dh_check_params_length()
68 return 0; in dh_set_params()
80 if (crypto_dh_decode_key(buf, len, &params) < 0) in dh_set_secret()
83 if (dh_set_params(ctx, &params) < 0) in dh_set_secret()
90 return 0; in dh_set_secret()
113 return 0; in dh_is_pubkey_valid()
126 if (mpi_cmp_ui(y, 1) < 1 || mpi_cmp(y, ctx->p) >= 0) in dh_is_pubkey_valid()
134 val = mpi_alloc(0); in dh_is_pubkey_valid()
[all …]
/linux/drivers/media/dvb-frontends/
H A Dstv0900_init.h24 { 0, 11101 }, /*C/N=-0dB*/
83 { -5, 0xCAA1 }, /*-5dBm*/
84 { -10, 0xC229 }, /*-10dBm*/
85 { -15, 0xBB08 }, /*-15dBm*/
86 { -20, 0xB4BC }, /*-20dBm*/
87 { -25, 0xAD5A }, /*-25dBm*/
88 { -30, 0xA298 }, /*-30dBm*/
89 { -35, 0x98A8 }, /*-35dBm*/
90 { -40, 0x8389 }, /*-40dBm*/
91 { -45, 0x59BE }, /*-45dBm*/
[all …]
H A Ditd1000.c31 } while (0)
35 } while (0)
39 } while (0)
46 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1 in itd1000_write_regs()
56 buf[0] = reg; in itd1000_write_regs()
59 /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */ in itd1000_write_regs()
65 return 0; in itd1000_write_regs()
72 { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 }, in itd1000_read_reg()
77 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1); in itd1000_read_reg()
100 { 0, 0x8, 0x3 },
[all …]
H A Dtda18271c2dd_maps.h3 HF_None = 0, HF_B, HF_DK, HF_G, HF_I, HF_L, HF_L1, HF_MN, HF_FM_Radio,
10 { 0, 0, 0x00, 0x00 }, /* HF_None */
11 { 6000000, 7000000, 0x1D, 0x2C }, /* HF_B, */
12 { 6900000, 8000000, 0x1E, 0x2C }, /* HF_DK, */
13 { 7100000, 8000000, 0x1E, 0x2C }, /* HF_G, */
14 { 7250000, 8000000, 0x1E, 0x2C }, /* HF_I, */
15 { 6900000, 8000000, 0x1E, 0x2C }, /* HF_L, */
16 { 1250000, 8000000, 0x1E, 0x2C }, /* HF_L1, */
17 { 5400000, 6000000, 0x1C, 0x2C }, /* HF_MN, */
18 { 1250000, 500000, 0x18, 0x2C }, /* HF_FM_Radio, */
[all …]
/linux/drivers/media/usb/gspca/
H A Dov534_9.c20 #define OV534_REG_ADDRESS 0xf1 /* sensor address */
21 #define OV534_REG_SUBADDR 0xf2
22 #define OV534_REG_WRITE 0xf3
23 #define OV534_REG_READ 0xf4
24 #define OV534_REG_OPERATION 0xf5
25 #define OV534_REG_STATUS 0xf6
27 #define OV534_OP_WRITE_3 0x37
28 #define OV534_OP_WRITE_2 0x33
29 #define OV534_OP_READ_2 0xf9
54 #define QVGA_MODE 0
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dt2081qds.dts104 #size-cells = <0>;
105 reg = <0x54 1>;
106 mux-mask = <0xe0>;
108 t2081mdio0: mdio@0 {
110 #size-cells = <0>;
111 reg = <0>;
114 reg = <0x1>;
120 #size-cells = <0>;
121 reg = <0x20>;
124 reg = <0x2>;
[all …]
/linux/drivers/infiniband/hw/qib/
H A Dqib_6120_regs.h35 #define QIB_6120_Revision_OFFS 0x0
36 #define QIB_6120_Revision_R_Simulator_LSB 0x3F
37 #define QIB_6120_Revision_R_Simulator_RMASK 0x1
38 #define QIB_6120_Revision_Reserved_LSB 0x28
39 #define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF
40 #define QIB_6120_Revision_BoardID_LSB 0x20
41 #define QIB_6120_Revision_BoardID_RMASK 0xFF
42 #define QIB_6120_Revision_R_SW_LSB 0x18
43 #define QIB_6120_Revision_R_SW_RMASK 0xFF
44 #define QIB_6120_Revision_R_Arch_LSB 0x10
[all …]
H A Dqib_7322_regs.h35 #define QIB_7322_Revision_OFFS 0x0
36 #define QIB_7322_Revision_DEF 0x0000000002010601
37 #define QIB_7322_Revision_R_Simulator_LSB 0x3F
38 #define QIB_7322_Revision_R_Simulator_MSB 0x3F
39 #define QIB_7322_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7322_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7322_Revision_R_Emulation_MSB 0x3E
42 #define QIB_7322_Revision_R_Emulation_RMASK 0x1
43 #define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x28
44 #define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D
[all …]
H A Dqib_7220_regs.h37 #define QIB_7220_Revision_OFFS 0x0
38 #define QIB_7220_Revision_R_Simulator_LSB 0x3F
39 #define QIB_7220_Revision_R_Simulator_RMASK 0x1
40 #define QIB_7220_Revision_R_Emulation_LSB 0x3E
41 #define QIB_7220_Revision_R_Emulation_RMASK 0x1
42 #define QIB_7220_Revision_R_Emulation_Revcode_LSB 0x28
43 #define QIB_7220_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF
44 #define QIB_7220_Revision_BoardID_LSB 0x20
45 #define QIB_7220_Revision_BoardID_RMASK 0xFF
46 #define QIB_7220_Revision_R_SW_LSB 0x18
[all …]
/linux/arch/x86/kernel/cpu/microcode/
H A Damd_shas.c3 { 0x8001227, {
4 0x99,0xc0,0x9b,0x2b,0xcc,0x9f,0x52,0x1b,
5 0x1a,0x5f,0x1d,0x83,0xa1,0x6c,0xc4,0x46,
6 0xe2,0x6c,0xda,0x73,0xfb,0x2d,0x23,0xa8,
7 0x77,0xdc,0x15,0x31,0x33,0x4a,0x46,0x18,
10 { 0x8001250, {
11 0xc0,0x0b,0x6b,0x19,0xfd,0x5c,0x39,0x60,
12 0xd5,0xc3,0x57,0x46,0x54,0xe4,0xd1,0xaa,
13 0xa8,0xf7,0x1f,0xa8,0x6a,0x60,0x3e,0xe3,
14 0x27,0x39,0x8e,0x53,0x30,0xf8,0x49,0x19,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_2_1_0_sh_mask.h27 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
28 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
29 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
30 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON__SHIFT 0x3
31 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
32 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
33 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
34 …_TX_CLOCK_CNTL__DPCS_SYMCLK_DIV2_CLOCK_ON_MASK 0x00000008L
36 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
37 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
H A Ddpcs_3_0_0_sh_mask.h14 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS__SHIFT 0x0
15 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_EN__SHIFT 0x1
16 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON__SHIFT 0x2
17 …0_DPCSTX_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON__SHIFT 0x3
18 …_TX_CLOCK_CNTL__DPCS_SYMCLK_GATE_DIS_MASK 0x00000001L
19 …_TX_CLOCK_CNTL__DPCS_SYMCLK_EN_MASK 0x00000002L
20 …_TX_CLOCK_CNTL__DPCS_SYMCLK_CLOCK_ON_MASK 0x00000004L
21 …_TX_CLOCK_CNTL__DPCS_TX_CLK_LDPCS_CLOCK_ON_MASK 0x00000008L
23 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_REQ__SHIFT 0xc
24 …0_DPCSTX_TX_CNTL__DPCS_TX_PLL_UPDATE_PENDING__SHIFT 0xd
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/pcie/
H A Dpcie_6_1_0_sh_mask.h29 …WDID__Hardware_Revision__SHIFT 0x0
30 …WDID__Hardware_Minor_Version_Number__SHIFT 0x6
31 …WDID__Hardware_Major_Version_Number__SHIFT 0xd
32 …rdware_Revision_MASK 0x0000003FL
33 …rdware_Minor_Version_Number_MASK 0x00001FC0L
34 …rdware_Major_Version_Number_MASK 0x000FE000L
36 …INKAGE_LANEGRP__Lane_Group_Indirect_Accesses__SHIFT 0x0
37 …INKAGE_LANEGRP__Lane_Group_Aperture_Size__SHIFT 0x2
38 …INKAGE_LANEGRP__Index_Offset__SHIFT 0x6
39 …NKAGE_LANEGRP__Presence__SHIFT 0x14
[all …]
/linux/drivers/video/fbdev/sis/
H A Doem300.h55 {0x08,0x08,0x08,0x08},
56 {0x08,0x08,0x08,0x08},
57 {0x08,0x08,0x08,0x08},
58 {0x2c,0x2c,0x2c,0x2c},
59 {0x08,0x08,0x08,0x08},
60 {0x08,0x08,0x08,0x08},
61 {0x08,0x08,0x08,0x08},
62 {0x20,0x20,0x20,0x20}
67 {0x20,0x20,0x20,0x20},
68 {0x20,0x20,0x20,0x20},
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-boe-th101mb31ig002-28a.c53 gpiod_direction_output(ctx->reset, 0); in boe_th101mb31ig002_reset()
57 gpiod_direction_output(ctx->reset, 0); in boe_th101mb31ig002_reset()
65 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0xab, 0xba); in boe_th101mb31ig002_enable()
66 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0xba, 0xab); in boe_th101mb31ig002_enable()
67 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb1, 0x10, 0x01, 0x47, 0xff); in boe_th101mb31ig002_enable()
68 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb2, 0x0c, 0x14, 0x04, 0x50, 0x50, 0x14); in boe_th101mb31ig002_enable()
69 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb3, 0x56, 0x53, 0x00); in boe_th101mb31ig002_enable()
70 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb4, 0x33, 0x30, 0x04); in boe_th101mb31ig002_enable()
71 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xb6, 0xb0, 0x00, 0x00, 0x10, 0x00, 0x10, in boe_th101mb31ig002_enable()
72 0x00); in boe_th101mb31ig002_enable()
[all …]
/linux/drivers/platform/x86/
H A Dmsi-ec.c50 .address = 0xef,
51 .offset_start = 0x8a,
52 .offset_end = 0x80,
53 .range_min = 0x8a,
54 .range_max = 0xe4,
57 .address = 0x2e,
58 .block_address = 0x2f,
62 .address = 0xbf,
66 .address = 0x98,
70 .address = 0xf2,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_4_0_3_sh_mask.h29 …P_CTRL__STANDARD__SHIFT 0x0
30 …P_CTRL__STD_VERSION__SHIFT 0x4
31 …STANDARD_MASK 0x0000000FL
32 …STD_VERSION_MASK 0x00000010L
34 …C_GATE__SYS__SHIFT 0x0
35 …C_GATE__UDEC__SHIFT 0x1
36 …C_GATE__MPEG2__SHIFT 0x2
37 …C_GATE__REGS__SHIFT 0x3
38 …C_GATE__RBC__SHIFT 0x4
39 …C_GATE__LMI_MC__SHIFT 0x5
[all …]
H A Dvcn_5_0_0_sh_mask.h29 …P_CTRL__STANDARD__SHIFT 0x0
30 …P_CTRL__STD_VERSION__SHIFT 0x4
31 …STANDARD_MASK 0x0000000FL
32 …STD_VERSION_MASK 0x00000010L
34 …C_GATE__SYS__SHIFT 0x0
35 …C_GATE__UDEC__SHIFT 0x1
36 …C_GATE__MPEG2__SHIFT 0x2
37 …C_GATE__REGS__SHIFT 0x3
38 …C_GATE__RBC__SHIFT 0x4
39 …C_GATE__LMI_MC__SHIFT 0x5
[all …]
/linux/lib/crypto/
H A Dblake2s-selftest.c28 * for (i = 0; i < len; i++) {
29 * if (i && (i % 12) == 0)
31 * printf("0x%02x, ", vec[i]);
43 * key[0] = key[1] = 1;
47 * for (i = 0; i < BLAKE2S_TESTVEC_COUNT; ++i)
52 * for (i = 0; i < BLAKE2S_TESTVEC_COUNT; ++i) {
62 * return 0;
66 { 0xa1, },
67 { 0x7c, 0x89, },
68 { 0x74, 0x0e, 0xd4, },
[all …]

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