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/linux/drivers/clk/mediatek/
H A Dclk-mt7988-topckgen.c107 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents, 0x000, 0x004, 0x008,
108 0, 2, 7, 0x1c0, 0),
109 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel", netsys_500m_parents, 0x000,
110 0x004, 0x008, 8, 2, 15, 0x1C0, 1),
111 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel", netsys_2x_parents, 0x000,
112 0x004, 0x008, 16, 2, 23, 0x1C0, 2),
113 MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_GSW_SEL, "netsys_gsw_sel", netsys_gsw_parents, 0x000,
114 0x004, 0x008, 24, 2, 31, 0x1C0, 3),
116 MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_GMII_SEL, "eth_gmii_sel", eth_gmii_parents, 0x010, 0x014,
117 0x018, 0, 1, 7, 0x1C0, 4),
[all …]
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcie-qhp.h10 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14
11 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20
12 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24
13 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28
14 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c
15 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34
16 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38
17 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54
18 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58
19 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v4_20.h10 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88
11 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c
12 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90
13 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4
14 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0
17 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008
18 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058
19 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac
20 #define QSERDES_V4_20_RX_DFE_3 0x110
21 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134
[all …]
H A Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
H A Dphy-qcom-qmp-pcs-v4.h10 #define QPHY_V4_PCS_SW_RESET 0x000
11 #define QPHY_V4_PCS_REVISION_ID0 0x004
12 #define QPHY_V4_PCS_REVISION_ID1 0x008
13 #define QPHY_V4_PCS_REVISION_ID2 0x00c
14 #define QPHY_V4_PCS_REVISION_ID3 0x010
15 #define QPHY_V4_PCS_PCS_STATUS1 0x014
16 #define QPHY_V4_PCS_PCS_STATUS2 0x018
17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
18 #define QPHY_V4_PCS_PCS_STATUS4 0x020
19 #define QPHY_V4_PCS_PCS_STATUS5 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx.h10 #define QSERDES_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_TX_BIST_INVERT 0x004
12 #define QSERDES_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_TX_CMN_CONTROL_ONE 0x00c
14 #define QSERDES_TX_CMN_CONTROL_TWO 0x010
15 #define QSERDES_TX_CMN_CONTROL_THREE 0x014
16 #define QSERDES_TX_TX_EMP_POST1_LVL 0x018
17 #define QSERDES_TX_TX_POST2_EMPH 0x01c
18 #define QSERDES_TX_TX_BOOST_LVL_UP_DN 0x020
19 #define QSERDES_TX_HP_PD_ENABLES 0x024
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H A Dphy-qcom-qmp-qserdes-txrx-v4.h10 #define QSERDES_V4_TX_BIST_MODE_LANENO 0x000
11 #define QSERDES_V4_TX_BIST_INVERT 0x004
12 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x008
13 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x00c
14 #define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP 0x010
15 #define QSERDES_V4_TX_TX_DRV_LVL 0x014
16 #define QSERDES_V4_TX_TX_DRV_LVL_OFFSET 0x018
17 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x01c
18 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x020
19 #define QSERDES_V4_TX_TX_BAND 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5.h11 #define QSERDES_V5_TX_BIST_MODE_LANENO 0x000
12 #define QSERDES_V5_TX_BIST_INVERT 0x004
13 #define QSERDES_V5_TX_CLKBUF_ENABLE 0x008
14 #define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c
15 #define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010
16 #define QSERDES_V5_TX_TX_DRV_LVL 0x014
17 #define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018
18 #define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c
19 #define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020
20 #define QSERDES_V5_TX_TX_BAND 0x024
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/linux/drivers/media/platform/chips-media/coda/
H A Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/linux/arch/arm/mach-s3c/
H A Dregs-gpio-memport-s3c64xx.h14 #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0)
15 #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4)
17 #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0)
18 #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4)
19 #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8)
21 #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0)
22 #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
/linux/arch/arm/boot/dts/ti/omap/
H A Dmotorola-mapphone-common.dtsi15 reg = <0x80000000 0x3fd00000>; /* 1021 MB */
21 pinctrl-0 = <&poweroff_gpio>;
28 pinctrl-0 = <&hdmi_hpd_gpio>;
118 pinctrl-0 = <&dss_hdmi_pins>;
125 lanes = <1 0 3 2 5 4 7 6>;
133 reg = <0x48>;
134 pinctrl-0 = <&tmp105_irq>;
138 &omap4_pmx_core 0x14e>;
158 pinctrl-0 = <&mmc3_pins>;
162 &omap4_pmx_core 0xde>;
[all …]
H A Domap5-uevm.dts15 reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
25 reg = <0 0x95000000 0 0x800000>;
32 reg = <0 0x95800000 0 0x3800000>;
56 pinctrl-0 = <&evm_keys_pins>;
59 #size-cells = <0>;
139 reg = <0x50>;
145 pinctrl-0 = <&i2c5_pins>;
151 reg = <0x22>;
159 pinctrl-0 = <&mmc1_pins>;
167 OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dti,iodelay.txt24 reg = <0x4844a000 0x0d1c>;
26 #size-cells = <0>;
35 0x18c A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A19_IN */
36 0x1a4 A_DELAY_PS(265) G_DELAY_PS(360) /* CFG_GPMC_A20_IN */
37 0x1b0 A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A21_IN */
38 0x1bc A_DELAY_PS(0) G_DELAY_PS(120) /* CFG_GPMC_A22_IN */
39 0x1c8 A_DELAY_PS(287) G_DELAY_PS(420) /* CFG_GPMC_A23_IN */
40 0x1d4 A_DELAY_PS(144) G_DELAY_PS(240) /* CFG_GPMC_A24_IN */
41 0x1e0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_IN */
42 0x1ec A_DELAY_PS(120) G_DELAY_PS(0) /* CFG_GPMC_A26_IN */
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
[all …]
/linux/arch/sh/include/mach-se/mach/
H A Dse7724.h21 #define SH_ETH_ADDR (0xA4600000)
22 #define SH_ETH_MAHR (SH_ETH_ADDR + 0x1C0)
23 #define SH_ETH_MALR (SH_ETH_ADDR + 0x1C8)
25 #define PA_LED (0xba203000) /* 8bit LED */
26 #define IRQ_MODE (0xba200010)
27 #define IRQ0_SR (0xba200014)
28 #define IRQ1_SR (0xba200018)
29 #define IRQ2_SR (0xba20001c)
30 #define IRQ0_MR (0xba200020)
31 #define IRQ1_MR (0xba200024)
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Dbranch.json4 "EventCode": "0x8b",
9 "EventCode": "0x8e",
14 "EventCode": "0x91",
19 "EventCode": "0xc2",
24 "EventCode": "0xc3",
29 "EventCode": "0xc4",
34 "EventCode": "0xc5",
39 "EventCode": "0xc6",
44 "EventCode": "0xc8",
49 "EventCode": "0xc9",
[all …]
/linux/drivers/usb/fotg210/
H A Dfotg210-udc.h14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-pic32.h12 #define ANSEL_REG 0x00
13 #define TRIS_REG 0x10
14 #define PORT_REG 0x20
15 #define LAT_REG 0x30
16 #define ODCU_REG 0x40
17 #define CNPU_REG 0x50
18 #define CNPD_REG 0x60
19 #define CNCON_REG 0x70
20 #define CNEN_REG 0x80
21 #define CNSTAT_REG 0x90
[all …]
/linux/include/dt-bindings/clock/
H A Domap5.h8 #define OMAP5_CLKCTRL_OFFSET 0x20
12 #define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
15 #define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
18 #define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
19 #define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
20 #define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
21 #define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
22 #define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
23 #define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
24 #define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
[all …]
H A Domap4.h8 #define OMAP4_CLKCTRL_OFFSET 0x20
12 #define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
15 #define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
18 #define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20)
19 #define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28)
20 #define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30)
21 #define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38)
22 #define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40)
23 #define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48)
24 #define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50)
[all …]
/linux/arch/arm/boot/dts/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drpm.h14 #define PCI_DEVID_CN10K_RPM 0xA060
15 #define PCI_SUBSYS_DEVID_CNF10KB_RPM 0xBC00
16 #define PCI_DEVID_CN10KB_RPM 0xA09F
19 #define RPMX_CMRX_CFG 0x00
20 #define RPMX_CMR_GLOBAL_CFG 0x08
24 #define RPMX_CMRX_RX_ID_MAP 0x80
25 #define RPMX_CMRX_SW_INT 0x180
26 #define RPMX_CMRX_SW_INT_W1S 0x188
27 #define RPMX_CMRX_SW_INT_ENA_W1S 0x198
28 #define RPMX_CMRX_LINK_CFG 0x1070
[all …]

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