Searched +full:0 +full:x1a140000 (Results 1 – 6 of 6) sorted by relevance
37 reg = <0x1a140000 0x1000>;
32 where N starting from 0 to one less than the number of root ports.80 reg = <0 0x1a000000 0 0x1000>;88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */89 <0 0x1a142000 0 0x1000>, /* Port0 registers */90 <0 0x1a143000 0 0x1000>, /* Port1 registers */91 <0 0x1a144000 0 0x1000>; /* Port2 registers */96 interrupt-map-mask = <0xf800 0 0 0>;97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;[all …]
24 #size-cells = <0>;27 cpu0: cpu@0 {30 reg = <0x0>;38 reg = <0x1>;51 clk20m: oscillator-0 {53 #clock-cells = <0>;60 #clock-cells = <0>;83 reg = <0x10000000 0x1000>;89 reg = <0x10002000 0x1000>;97 reg = <0x10006000 0x1000>;[all …]
73 #size-cells = <0>;76 cpu0: cpu@0 {79 reg = <0x0>;91 reg = <0x1>;103 reg = <0x2>;115 reg = <0x3>;137 #clock-cells = <0>;142 #clock-cells = <0>;147 clk26m: oscillator-0 {149 #clock-cells = <0>;[all …]
69 #size-cells = <0>;71 cpu0: cpu@0 {74 reg = <0x0 0x0>;89 reg = <0x0 0x1>;111 #clock-cells = <0>;116 #clock-cells = <0>;140 reg = <0 0x43000000 0 0x30000>;150 thermal-sensors = <&thermal 0>;216 reg = <0 0x10000000 0 0x1000>;223 reg = <0 0x10001000 0 0x250>;[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]