Searched +full:0 +full:x1a00000 (Results 1 – 8 of 8) sorted by relevance
14 cell-index = <0>;16 ranges = <0x0 0x0 0x1a00000 0xfe000>;17 reg = <0x0 0x1a00000 0x0 0xfe000>;20 clocks = <&clockgen QORIQ_CLK_FMAN 0>;22 fsl,qman-channel-range = <0x800 0x10>;26 muram@0 {28 reg = <0x0 0x60000>;32 cell-index = <0x2>;34 reg = <0x82000 0x1000>;38 cell-index = <0x3>;[all …]
17 ranges = <0x70000000 0x70000000 0x50000000>,18 <0x00000000 0xd0000000 0x20000000>;19 dma-ranges = <0x0 0x20000000 0x40000000>;22 reg = <0x70000000 0x1000>;28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;32 reg = <0x0 0x1000 0x0 0x1000>;40 reg = <0x90000000 0x1000>;41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,[all …]
20 reg = <0x84000000 0xA00000>;25 reg = <0x84B00000 0x100000>;30 reg = <0x85000000 0x1A00000>;35 reg = <0x86B00000 0x100000>;40 reg = <0x86D00000 0x100000>;51 #size-cells = <0>;64 cpu0: cpu@0 {67 reg = <0x0>;76 reg = <0x1>;91 reg = <0x1fa20000 0x400>,[all …]
26 qcom,msm-id = <251 0>, <252 0>;27 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;47 reg = <0x0 0x1ff00000 0x0 0x40000>;48 console-size = <0x10000>;49 record-size = <0x10000>;50 ftrace-size = <0x10000>;51 pmsg-size = <0x20000>;55 reg = <0 0x03400000 0 0xc00000>;60 reg = <0x0 0x05000000 0x0 0x1a00000>;71 pm8994_regulators: regulators-0 {
24 qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */25 qcom,board-id = <8 0>;34 reg = <0 0xa7f00000 0 0x100000>;35 record-size = <0x20000>;36 console-size = <0x40000>;37 ftrace-size = <0x20000>;38 pmsg-size = <0x20000>;43 reg = <0x0 0x8ea00000 0x0 0x1a00000>;49 reg = <0x0 0x90400000 0x0 0x2000>;54 reg = <0 0x90500000 0 0xa00000>;[all …]
20 reg = <0x0 0x84000000 0x0 0xa00000>;25 reg = <0x0 0x84b00000 0x0 0x100000>;30 reg = <0x0 0x85000000 0x0 0x1a00000>;35 reg = <0x0 0x86b00000 0x0 0x100000>;40 reg = <0x0 0x86d00000 0x0 0x100000>;51 #size-cells = <0>;73 cpu0: cpu@0 {76 reg = <0x0>;85 reg = <0x1>;94 reg = <0x2>;[all …]
28 * 0x2000000 (32M) +-----------------------------------------+30 * 0x1F80000 (31.5M) +-----------------------------------------+32 * 0x1C00000 (30M) +-----------------------------------------+34 * 0x0800000 (28M) +-----------------------------------------+36 * 0x1B00000 (27M) +-----------------------------------------+38 * 0x1A00000 (26M) +-----------------------------------------+40 * 0x1800000 (24M) +-----------------------------------------+42 * 0x1600000 (22M) +-----------------------------------------+48 * 0x190000 (2M--) +-----------------------------------------+51 * 0x34000 (208K) +-----------------------------------------+[all …]
12 #define RVU_AF_MSIXTR_BASE (0x10)13 #define RVU_AF_ECO (0x20)14 #define RVU_AF_BLK_RST (0x30)15 #define RVU_AF_PF_BAR4_ADDR (0x40)16 #define RVU_AF_RAS (0x100)17 #define RVU_AF_RAS_W1S (0x108)18 #define RVU_AF_RAS_ENA_W1S (0x110)19 #define RVU_AF_RAS_ENA_W1C (0x118)20 #define RVU_AF_GEN_INT (0x120)21 #define RVU_AF_GEN_INT_W1S (0x128)[all …]