Searched +full:0 +full:x1947 (Results 1 – 20 of 20) sorted by relevance
26 #define ixATTR00 0x000027 #define ixATTR01 0x000128 #define ixATTR02 0x000229 #define ixATTR03 0x000330 #define ixATTR04 0x000431 #define ixATTR05 0x000532 #define ixATTR06 0x000633 #define ixATTR07 0x000734 #define ixATTR08 0x000835 #define ixATTR09 0x0009[all …]
27 #define mmPIPE0_PG_CONFIG 0x176028 #define mmPIPE0_PG_ENABLE 0x176129 #define mmPIPE0_PG_STATUS 0x176230 #define mmPIPE1_PG_CONFIG 0x176431 #define mmPIPE1_PG_ENABLE 0x176532 #define mmPIPE1_PG_STATUS 0x176633 #define mmPIPE2_PG_CONFIG 0x176834 #define mmPIPE2_PG_ENABLE 0x176935 #define mmPIPE2_PG_STATUS 0x176a36 #define mmPIPE3_PG_CONFIG 0x176c[all …]
27 // base address: 0x4828 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x001229 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 033 // base address: 0x4c34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x001435 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 039 // base address: 0x040 …DC_PERFMON0_PERFCOUNTER_CNTL 0x002042 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x002144 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022[all …]
29 // base address: 0x498030 …SDMA0_DEC_START 0x000031 …e regSDMA0_DEC_START_BASE_IDX 032 …SDMA0_MCU_MISC_CNTL 0x000133 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 034 …SDMA0_UCODE_REV 0x000335 …e regSDMA0_UCODE_REV_BASE_IDX 036 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000537 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 038 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006[all …]
27 // base address: 0x4828 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 035 // base address: 0x3b436 …CRTC8_IDX 0x002d38 …CRTC8_DATA 0x002d40 …GENFC_WT 0x002e42 …GENS1 0x002e[all …]
27 // base address: 0x028 …DENTIST_DISPCLK_CNTL 0x006433 // base address: 0x034 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x004036 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x004138 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x004240 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x004342 …DP_DTO_DBUF_EN 0x004444 …DSCCLK3_DTO_PARAM 0x004546 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048[all …]
27 // base address: 0x130000031 // base address: 0x130000035 // base address: 0x130000039 // base address: 0x130000043 // base address: 0x130000047 // base address: 0x130002051 // base address: 0x130004055 // base address: 0x130006059 // base address: 0x130008063 // base address: 0x13000a0[all …]
11 // base address: 0x012 …DENTIST_DISPCLK_CNTL 0x006417 // base address: 0x018 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x004020 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x004122 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x004224 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x004326 …DP_DTO_DBUF_EN 0x004428 …DSCCLK3_DTO_PARAM 0x004530 …DSCCLK4_DTO_PARAM 0x0046[all …]
27 // base address: 0x028 …VGA_MEM_WRITE_PAGE_ADDR 0x000029 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 030 …VGA_MEM_READ_PAGE_ADDR 0x000131 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 032 …VGA_RENDER_CONTROL 0x000034 …VGA_SEQUENCER_RESET_CONTROL 0x000136 …VGA_MODE_CONTROL 0x000238 …VGA_SURFACE_PITCH_SELECT 0x000340 …VGA_MEMORY_BASE_ADDRESS 0x0004[all …]
30 // base address: 0x130000031 …CONTROLLER0_GLOBAL_CAPABILITIES 0x4b700033 …CONTROLLER0_MINOR_VERSION 0x4b700035 …CONTROLLER0_MAJOR_VERSION 0x4b700037 …CONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b700139 …CONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b700141 …CONTROLLER0_GLOBAL_CONTROL 0x4b700243 …CONTROLLER0_WAKE_ENABLE 0x4b700345 …CONTROLLER0_STATE_CHANGE_STATUS 0x4b700347 …CONTROLLER0_GLOBAL_STATUS 0x4b7004[all …]
31 // base address: 0x032 …AZCONTROLLER0_CORB_WRITE_POINTER 0x000033 …e regAZCONTROLLER0_CORB_WRITE_POINTER_BASE_IDX 034 …AZCONTROLLER0_CORB_READ_POINTER 0x000035 …e regAZCONTROLLER0_CORB_READ_POINTER_BASE_IDX 036 …AZCONTROLLER0_CORB_CONTROL 0x000137 …e regAZCONTROLLER0_CORB_CONTROL_BASE_IDX 038 …AZCONTROLLER0_CORB_STATUS 0x000139 …e regAZCONTROLLER0_CORB_STATUS_BASE_IDX 040 …AZCONTROLLER0_CORB_SIZE 0x0001[all …]
7 // base address: 0x13000008 …OBAL_CAPABILITIES 0x4b700010 …NOR_VERSION 0x4b700012 …JOR_VERSION 0x4b700014 …TPUT_PAYLOAD_CAPABILITY 0x4b700116 …PUT_PAYLOAD_CAPABILITY 0x4b700118 …OBAL_CONTROL 0x4b700220 …KE_ENABLE 0x4b700322 …ATE_CHANGE_STATUS 0x4b700324 …OBAL_STATUS 0x4b7004[all …]
28 // base address: 0x130000029 …OBAL_CAPABILITIES 0x4b700031 …NOR_VERSION 0x4b700033 …JOR_VERSION 0x4b700035 …TPUT_PAYLOAD_CAPABILITY 0x4b700137 …PUT_PAYLOAD_CAPABILITY 0x4b700139 …OBAL_CONTROL 0x4b700241 …KE_ENABLE 0x4b700343 …ATE_CHANGE_STATUS 0x4b700345 …OBAL_STATUS 0x4b7004[all …]
27 // base address: 0x028 …DENTIST_DISPCLK_CNTL 0x006433 // base address: 0x034 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x004036 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x004138 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x004240 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x004342 …DP_DTO_DBUF_EN 0x004444 …DPREFCLK_CGTT_BLK_CTRL_REG 0x004846 …DCCG_GATE_DISABLE_CNTL4 0x0049[all …]
27 // base address: 0x130000028 …CONTROLLER0_GLOBAL_CAPABILITIES 0x4b700030 …CONTROLLER0_MINOR_VERSION 0x4b700032 …CONTROLLER0_MAJOR_VERSION 0x4b700034 …CONTROLLER0_OUTPUT_PAYLOAD_CAPABILITY 0x4b700136 …CONTROLLER0_INPUT_PAYLOAD_CAPABILITY 0x4b700138 …CONTROLLER0_GLOBAL_CONTROL 0x4b700240 …CONTROLLER0_WAKE_ENABLE 0x4b700342 …CONTROLLER0_STATE_CHANGE_STATUS 0x4b700344 …CONTROLLER0_GLOBAL_STATUS 0x4b7004[all …]
8 // base address: 0x09 …VGA_MEM_WRITE_PAGE_ADDR 0x000010 …VGA_MEM_WRITE_PAGE_ADDR 0x000011 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 012 …VGA_MEM_READ_PAGE_ADDR 0x000113 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 014 …VGA_RENDER_CONTROL 0x000016 …VGA_SEQUENCER_RESET_CONTROL 0x000118 …VGA_MODE_CONTROL 0x000220 …VGA_SURFACE_PITCH_SELECT 0x0003[all …]
52 static const hda_nid_t alc269_ignore[] = { 0x1d, 0 }; in alc269_parse_auto_config()53 static const hda_nid_t alc269_ssids[] = { 0, 0x1b, 0x14, 0x21 }; in alc269_parse_auto_config()54 static const hda_nid_t alc269va_ssids[] = { 0x15, 0x1b, 0x14, 0 }; in alc269_parse_auto_config()104 int report = 0; in alc_headset_btn_callback()131 case 0x10ec0215: in alc_disable_headset_jack_key()132 case 0x10ec0225: in alc_disable_headset_jack_key()133 case 0x10ec0285: in alc_disable_headset_jack_key()134 case 0x10ec0287: in alc_disable_headset_jack_key()135 case 0x10ec0295: in alc_disable_headset_jack_key()136 case 0x10ec0289: in alc_disable_headset_jack_key()[all …]