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/linux/drivers/regulator/
H A Dslg51000-regulator.h14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Deeprom.h131 /* common and choice range (0x0000 - 0x0fff) */
132 #define PDR_END 0x0000
133 #define PDR_MANUFACTURING_PART_NUMBER 0x0001
134 #define PDR_PDA_VERSION 0x0002
135 #define PDR_NIC_SERIAL_NUMBER 0x0003
136 #define PDR_NIC_RAM_SIZE 0x0005
137 #define PDR_RFMODEM_SUP_RANGE 0x0006
138 #define PDR_PRISM_MAC_SUP_RANGE 0x0007
139 #define PDR_NIC_ID 0x0008
141 #define PDR_MAC_ADDRESS 0x0101
[all …]
/linux/drivers/usb/serial/
H A Dcp210x.c54 { USB_DEVICE(0x0404, 0x034C) }, /* NCR Retail IO Box */
55 { USB_DEVICE(0x045B, 0x0053) }, /* Renesas RX610 RX-Stick */
56 { USB_DEVICE(0x0471, 0x066A) }, /* AKTAKOM ACE-1001 cable */
57 { USB_DEVICE(0x0489, 0xE000) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */
58 { USB_DEVICE(0x0489, 0xE003) }, /* Pirelli Broadband S.p.A, DP-L10 SIP/GSM Mobile */
59 { USB_DEVICE(0x04BF, 0x1301) }, /* TDK Corporation NC0110013M - Network Controller */
60 { USB_DEVICE(0x04BF, 0x1303) }, /* TDK Corporation MM0110113M - i3 Micro Module */
61 { USB_DEVICE(0x0745, 0x1000) }, /* CipherLab USB CCD Barcode Scanner 1000 */
62 …{ USB_DEVICE(0x0846, 0x1100) }, /* NetGear Managed Switch M4100 series, M5300 series, M7100 series…
63 { USB_DEVICE(0x08e6, 0x5501) }, /* Gemalto Prox-PU/CU contactless smartcard reader */
[all …]
H A Dftdi_sio_ids.h17 #define FTDI_VID 0x0403 /* Vendor Id */
22 #define FTDI_8U232AM_PID 0x6001 /* Similar device to SIO above */
23 #define FTDI_8U232AM_ALT_PID 0x6006 /* FTDI's alternate PID for above */
24 #define FTDI_8U2232C_PID 0x6010 /* Dual channel device */
25 #define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */
26 #define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */
27 #define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */
28 #define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */
29 #define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */
30 #define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */
[all …]
H A Doption.c51 #define OPTION_VENDOR_ID 0x0AF0
52 #define OPTION_PRODUCT_COLT 0x5000
53 #define OPTION_PRODUCT_RICOLA 0x6000
54 #define OPTION_PRODUCT_RICOLA_LIGHT 0x6100
55 #define OPTION_PRODUCT_RICOLA_QUAD 0x6200
56 #define OPTION_PRODUCT_RICOLA_QUAD_LIGHT 0x6300
57 #define OPTION_PRODUCT_RICOLA_NDIS 0x6050
58 #define OPTION_PRODUCT_RICOLA_NDIS_LIGHT 0x6150
59 #define OPTION_PRODUCT_RICOLA_NDIS_QUAD 0x6250
60 #define OPTION_PRODUCT_RICOLA_NDIS_QUAD_LIGHT 0x6350
[all …]
/linux/drivers/acpi/nfit/
H A Dnfit.h20 #define UUID_NFIT_DIMM "4309ac30-0d11-11e4-9191-0800200c9a66"
30 /* http://www.uefi.org/RFIC_LIST (see "Virtual NVDIMM 0x1901") */
131 #define NFIT_FIC_BYTE cpu_to_le16(0x101) /* byte-addressable energy backed */
132 #define NFIT_FIC_BLK cpu_to_le16(0x201) /* block-addressable non-energy backed */
133 #define NFIT_FIC_BYTEN cpu_to_le16(0x301) /* byte-addressable non-energy backed */
138 NFIT_ARS_STATUS_DONE = 0,
149 NFIT_NOTIFY_UPDATE = 0x80,
150 NFIT_NOTIFY_UC_MEMORY_ERROR = 0x81,
154 NFIT_NOTIFY_DIMM_HEALTH = 0x81,
/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml116 enum: [0, 1]
283 reg = <0x18800000 0x800000>;
300 iommus = <&anoc2_smmu 0x1900>,
301 <&anoc2_smmu 0x1901>;
310 iommus = <&apps_smmu 0x1c02 0x1>;
320 reg = <0xa000000 0x200000>;
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_drm.c75 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
96 static int nouveau_noaccel = 0;
100 "0 = disabled, 1 = enabled, 2 = headless)");
105 static int nouveau_atomic = 0;
108 MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
271 if (ret < 0) { in nouveau_cli_init()
283 if (ret < 0) { in nouveau_cli_init()
304 return 0; in nouveau_cli_init()
324 int ret = 0; in nouveau_accel_ce_init()
377 NULL, 0, &drm->channel->nvsw); in nouveau_accel_gr_init()
[all …]
/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc19 module_model_id 0x0000 16
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
22 pixel_order 0x0006 8
23 - e GRBG 0
27 MIPI_CCS_version 0x0007 8
28 - e v1_0 0x10
29 - e v1_1 0x11
31 - f minor 0 3
32 data_pedestal 0x0008 16
[all …]
/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h19 #define SMIAPP_REG_U16_MODEL_ID CCI_REG16(0x0000)
20 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
21 #define SMIAPP_REG_U8_MANUFACTURER_ID CCI_REG8(0x0003)
22 #define SMIAPP_REG_U8_SMIA_VERSION CCI_REG8(0x0004)
23 #define SMIAPP_REG_U8_FRAME_COUNT CCI_REG8(0x0005)
24 #define SMIAPP_REG_U8_PIXEL_ORDER CCI_REG8(0x0006)
25 #define SMIAPP_REG_U16_DATA_PEDESTAL CCI_REG16(0x0008)
26 #define SMIAPP_REG_U8_PIXEL_DEPTH CCI_REG8(0x000c)
27 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR CCI_REG8(0x0010)
28 #define SMIAPP_REG_U8_SMIAPP_VERSION CCI_REG8(0x0011)
[all …]
H A Dccs-regs.h20 #define CCS_R_MODULE_MODEL_ID CCI_REG16(0x0000)
21 #define CCS_R_MODULE_REVISION_NUMBER_MAJOR CCI_REG8(0x0002)
22 #define CCS_R_FRAME_COUNT CCI_REG8(0x0005)
23 #define CCS_R_PIXEL_ORDER CCI_REG8(0x0006)
24 #define CCS_PIXEL_ORDER_GRBG 0U
28 #define CCS_R_MIPI_CCS_VERSION CCI_REG8(0x0007)
29 #define CCS_MIPI_CCS_VERSION_V1_0 0x10
30 #define CCS_MIPI_CCS_VERSION_V1_1 0x11
32 #define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0
33 #define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
[all …]
/linux/arch/x86/include/asm/
H A Dmsr-index.h10 #define MSR_EFER 0xc0000080 /* extended feature register */
11 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
12 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
13 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
14 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
15 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
16 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
17 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
18 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
21 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
[all …]
/linux/tools/arch/x86/include/asm/
H A Dmsr-index.h10 #define MSR_EFER 0xc0000080 /* extended feature register */
11 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
12 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
13 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
14 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
15 #define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
16 #define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
17 #define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
18 #define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
21 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
[all …]
/linux/drivers/scsi/
H A Dsense_codes.h7 SENSE_CODE(0x0000, "No additional sense information")
8 SENSE_CODE(0x0001, "Filemark detected")
9 SENSE_CODE(0x0002, "End-of-partition/medium detected")
10 SENSE_CODE(0x0003, "Setmark detected")
11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected")
12 SENSE_CODE(0x0005, "End-of-data detected")
13 SENSE_CODE(0x0006, "I/O process terminated")
14 SENSE_CODE(0x0007, "Programmable early warning detected")
15 SENSE_CODE(0x0011, "Audio play operation in progress")
16 SENSE_CODE(0x0012, "Audio play operation paused")
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_registers.h18 #define VPP2_DUMMY_DATA 0x1900
19 #define VPP2_LINE_IN_LENGTH 0x1901
20 #define VPP2_PIC_IN_HEIGHT 0x1902
21 #define VPP2_SCALE_COEF_IDX 0x1903
22 #define VPP2_SCALE_COEF 0x1904
23 #define VPP2_VSC_REGION12_STARTP 0x1905
24 #define VPP2_VSC_REGION34_STARTP 0x1906
25 #define VPP2_VSC_REGION4_ENDP 0x1907
26 #define VPP2_VSC_START_PHASE_STEP 0x1908
27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909
[all …]
/linux/drivers/usb/class/
H A Dcdc-acm.c93 minor = idr_alloc(&acm_minors, acm, 0, ACM_TTY_MINORS, GFP_KERNEL); in acm_alloc_minor()
120 retval = usb_control_msg(acm->dev, usb_sndctrlpipe(acm->dev, 0), in acm_ctrl_msg()
122 acm->control->altsetting[0].desc.bInterfaceNumber, in acm_ctrl_msg()
126 "%s - rq 0x%02x, val %#x, len %#x, result %d\n", in acm_ctrl_msg()
131 return retval < 0 ? retval : 0; in acm_ctrl_msg()
143 control, NULL, 0); in acm_set_control()
147 acm_ctrl_msg(acm, USB_CDC_REQ_SET_LINE_CODING, 0, line, sizeof *(line))
149 acm_ctrl_msg(acm, USB_CDC_REQ_SEND_BREAK, ms, NULL, 0)
156 for (i = 0; i < ACM_NW; i++) in acm_poison_urbs()
158 for (i = 0; i < acm->rx_buflimit; i++) in acm_poison_urbs()
[all …]
/linux/sound/usb/
H A Dquirks.c42 for (quirk = quirk_comp->data; quirk->ifnum >= 0; ++quirk) { in create_composite_quirk()
50 if (err < 0) in create_composite_quirk()
54 for (quirk = quirk_comp->data; quirk->ifnum >= 0; ++quirk) { in create_composite_quirk()
62 if (err < 0) in create_composite_quirk()
67 return 0; in create_composite_quirk()
75 return 0; in ignore_interface_quirk()
84 return snd_usb_midi_v2_create(chip, intf, quirk, 0); in create_any_midi_quirk()
99 alts = &iface->altsetting[0]; in create_standard_audio_quirk()
102 if (err < 0) { in create_standard_audio_quirk()
108 usb_set_interface(chip->dev, altsd->bInterfaceNumber, 0); in create_standard_audio_quirk()
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8998.dtsi16 qcom,msm-id = <292 0x0>;
26 reg = <0x0 0x80000000 0x0 0x0>;
35 reg = <0x0 0x85800000 0x0 0x600000>;
40 reg = <0x0 0x85e00000 0x0 0x100000>;
45 reg = <0x0 0x86000000 0x0 0x200000>;
50 reg = <0x0 0x86200000 0x0 0x2d00000>;
56 reg = <0x0 0x88f00000 0x0 0x200000>;
64 reg = <0x0 0x8ab00000 0x0 0x700000>;
69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
/linux/drivers/input/joystick/
H A Dxpad.c80 #define MAP_DPAD_TO_BUTTONS (1 << 0)
90 #define XTYPE_XBOX 0
101 #define PKT_XB 0
131 { 0x0079, 0x18d4, "GPD Win 2 X-Box Controller", 0, XTYPE_XBOX360 },
132 { 0x03eb, 0xff01, "Wooting One (Legacy)", 0, XTYPE_XBOX360 },
133 { 0x03eb, 0xff02, "Wooting Two (Legacy)", 0, XTYPE_XBOX360 },
134 { 0x03f0, 0x038D, "HyperX Clutch", 0, XTYPE_XBOX360 }, /* wired */
135 { 0x03f0, 0x048D, "HyperX Clutch", 0, XTYPE_XBOX360 }, /* wireless */
136 { 0x03f0, 0x0495, "HyperX Clutch Gladiate", 0, XTYPE_XBOXONE },
137 { 0x03f0, 0x07A0, "HyperX Clutch Gladiate RGB", 0, XTYPE_XBOXONE },
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dtables_nphy.c19 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
20 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
21 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
22 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
23 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
24 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
25 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
26 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
27 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
28 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_VERSION 0x000d
35 …e regSDMA0_UCODE_VERSION_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
[all …]
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]

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