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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mq-nitrogen.dts21 reg = <0x00000000 0x40000000 0 0x80000000>;
27 pinctrl-0 = <&pinctrl_gpio_keys>;
53 pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
61 reg_vref_0v9: regulator-vref-0v9 {
63 regulator-name = "vref-0v9";
103 pinctrl-0 = <&pinctrl_fec1>;
111 #size-cells = <0>;
[all...]
H A Dimx8mp-msc-sm2s-ep1.dts55 pinctrl-0 = <&pinctrl_hdmi>;
70 reg = <0x0a>;
76 #sound-dai-cells = <0>;
84 /* I2S-0 = sai2 */
87 pinctrl-0 = <&pinctrl_sai2>;
111 pinctrl-0 = <&pinctrl_smarc_gpio>;
115 MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
116 MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
117 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
118 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10
[all …]
H A Dimx8mq-kontron-pitx-imx8m.dts36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 pinctrl-0 = <&pinctrl_reg_usdhc2>;
61 #size-cells = <0>;
63 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
67 tpm@0 {
69 reg = <0>;
76 pinctrl-0 = <&pinctrl_fec1>;
84 #size-cells = <0>;
86 ethphy0: ethernet-phy@0 {
[all …]
H A Dimx8mq-thor96.dts21 reg = <0x00000000 0x40000000 0 0x80000000>;
27 pinctrl-0 = <&pinctrl_leds>;
64 gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
93 pinctrl-0 = <&pinctrl_reg_usdhc2>;
109 pinctrl-0 = <&pinctrl_wifi_reg_on>;
117 pinctrl-0 = <&pinctrl_ecspi2>;
123 pinctrl-0 = <&pinctrl_fec1>;
131 #size-cells = <0>;
145 pinctrl-0 = <&pinctrl_i2c1>;
150 reg = <0x8>;
[all …]
H A Dimx8mm-venice-gw7903.dts32 reg = <0x0 0x40000000 0 0x80000000>;
48 interrupts = <0>;
76 pinctrl-0 = <&pinctrl_gpio_leds>;
78 led-0 {
177 #clock-cells = <0>;
228 pinctrl-0 = <&pinctrl_fec1>;
236 #size-cells = <0>;
238 ethphy0: ethernet-phy@0 {
240 reg = <0>;
271 pinctrl-0 = <&pinctrl_i2c1>;
[all …]
/linux/arch/arm64/kernel/
H A Dsmccc-call.S12 \instr #0
49 stp x1, x19, [sp, #-16]!
52 mov x19, x0
55 ldp x0, x1, [x19, #ARM_SMCCC_1_2_REGS_X0_OFFS]
56 ldp x2, x3, [x19, #ARM_SMCCC_1_2_REGS_X2_OFFS]
57 ldp x4, x5, [x19, #ARM_SMCCC_1_2_REGS_X4_OFFS]
58 ldp x6, x7, [x19, #ARM_SMCCC_1_2_REGS_X6_OFFS]
59 ldp x8, x9, [x19, #ARM_SMCCC_1_2_REGS_X8_OFFS]
60 ldp x10, x11, [x19, #ARM_SMCCC_1_2_REGS_X10_OFFS]
61 ldp x12, x13, [x19, #ARM_SMCCC_1_2_REGS_X12_OFFS]
[all …]
H A Dhead.S41 #if (PAGE_OFFSET & 0x1fffff) != 0
63 .quad 0 // Image load offset from start of RAM, little-endian
66 .quad 0 // reserved
67 .quad 0 // reserved
68 .quad 0 // reserved
81 * x19 primary_entry() .. start_kernel() whether we entered with the MMU on
101 cbnz x19, 0f
114 0: adrp x0, __idmap_text_start
119 1: mov x0, x19
135 mrs x19, CurrentEL
[all …]
H A Dhibernate-asm.S44 * x4: physical address of __hyp_stub_vectors, or 0
61 mov x19, x3
63 1: ldr x10, [x19, #HIBERN_PBE_ORIG]
65 ldr x1, [x19, #HIBERN_PBE_ADDR]
80 ldr x19, [x19, #HIBERN_PBE_NEXT]
81 cbnz x19, 1b
94 hvc #0
H A Dentry.S34 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
42 .if \el == 0
65 tbnz x0, #THREAD_SHIFT, 0f
70 0:
125 nop // Patched to SMC/HVC #0
209 .if \el == 0
215 stp x0, x1, [sp, #16 * 0]
224 stp x18, x19, [sp, #16 * 9]
231 .if \el == 0
241 ldr x19, [tsk, #TSK_TI_FLAGS]
[all …]
/linux/drivers/net/wan/
H A Dwanxlfw.inc_shipped2 0x60,0x00,0x00,0x16,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0xB9,0x40,0x00,0x00,0x00,0x00,0x00,
4 0x10,0x14,0x42,0x80,0x4A,0xB0,0x09,0xB0,0x00,0x00,0x10,0x04,0x67,0x00,0x00,0x0E,
5 0x06,0xB0,0x40,0x00,0x00,0x00,0x09,0xB0,0x00,0x00,0x10,0x04,0x58,0x80,0x0C,0x80,
6 0x00,0x00,0x00,0x10,0x66,0x00,0xFF,0xDE,0x21,0xFC,0x00,0x00,0x16,0xBC,0x00,0x6C,
7 0x21,0xFC,0x00,0x00,0x17,0x5E,0x01,0x00,0x21,0xFC,0x00,0x00,0x16,0xDE,0x01,0x78,
8 0x21,0xFC,0x00,0x00,0x16,0xFE,0x01,0x74,0x21,0xFC,0x00,0x00,0x17,0x1E,0x01,0x70,
9 0x21,0xFC,0x00,0x00,0x17,0x3E,0x01,0x6C,0x21,0xFC,0x00,0x00,0x18,0x4C,0x02,0x00,
10 0x23,0xFC,0x78,0x00,0x00,0x00,0xFF,0xFC,0x15,0x48,0x33,0xFC,0x04,0x80,0xFF,0xFC,
11 0x10,0x26,0x33,0xFC,0x01,0x10,0xFF,0xFC,0x10,0x2A,0x23,0xFC,0x00,0xD4,0x9F,0x40,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_4_1_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_2_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_1_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_1_8_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_3_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_2_0_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_1_7_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
/linux/drivers/video/fbdev/
H A Dplatinumfb.h54 * F = 14.3MHz * c0 / (c1 & 0x1f) / (1 << (c1 >> 5))
55 * Newer ones use the values in clocksel[0], for which the formula
57 * F = 15MHz * c0 / ((c1 & 0x1f) + 2) / (1 << (c1 >> 5))
69 #define DIV2 0x20
70 #define DIV4 0x40
71 #define DIV8 0x60
72 #define DIV16 0x80
76 0x5c00,
78 { 0xffc, 4, 0, 0, 0, 0, 0x428, 0,
79 0, 0xb3, 0xd3, 0x12, 0x1a5, 0x23, 0x28, 0x2d,
[all …]
/linux/lib/crypto/
H A Dcurve25519-fiat32.c18 * entries t[0]...t[9], represents the integer t[0]+2^26 t[1]+2^51 t[2]+2^77
41 h[0] = a0&((1<<26)-1); /* 26 used, 32-26 left. 26 */ in fe_frombytes_impl()
104 t = -!!t; /* all set if nonzero, 0 if 0 */ in cmovznz32()
119 { const u32 x2 = in1[0]; in fe_freeze()
120 { u32 x20; u8/*bool*/ x21 = subborrow_u26(0x0, x2, 0x3ffffed, &x20); in fe_freeze()
121 { u32 x23; u8/*bool*/ x24 = subborrow_u25(x21, x4, 0x1ffffff, &x23); in fe_freeze()
122 { u32 x26; u8/*bool*/ x27 = subborrow_u26(x24, x6, 0x3ffffff, &x26); in fe_freeze()
123 { u32 x29; u8/*bool*/ x30 = subborrow_u25(x27, x8, 0x1ffffff, &x29); in fe_freeze()
124 { u32 x32; u8/*bool*/ x33 = subborrow_u26(x30, x10, 0x3ffffff, &x32); in fe_freeze()
125 { u32 x35; u8/*bool*/ x36 = subborrow_u25(x33, x12, 0x1ffffff, &x35); in fe_freeze()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/athub/
H A Dathub_3_0_0_sh_mask.h29 …R_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
30 …RTR0__BASE_ADDR_MASK 0x7FFFFFFFL
32 …R_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
33 …RTR1__BASE_ADDR_MASK 0x7FFFFFFFL
35 …R_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
36 …RTR2__BASE_ADDR_MASK 0x7FFFFFFFL
38 …R_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
39 …RTR3__BASE_ADDR_MASK 0x7FFFFFFFL
41 …R_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
42 …RTR4__BASE_ADDR_MASK 0x7FFFFFFFL
[all …]
H A Dathub_4_1_0_sh_mask.h29 …R_SRC_APRTR0__BASE_ADDR__SHIFT 0x0
30 …RTR0__BASE_ADDR_MASK 0x7FFFFFFFL
32 …R_SRC_APRTR1__BASE_ADDR__SHIFT 0x0
33 …RTR1__BASE_ADDR_MASK 0x7FFFFFFFL
35 …R_SRC_APRTR2__BASE_ADDR__SHIFT 0x0
36 …RTR2__BASE_ADDR_MASK 0x7FFFFFFFL
38 …R_SRC_APRTR3__BASE_ADDR__SHIFT 0x0
39 …RTR3__BASE_ADDR_MASK 0x7FFFFFFFL
41 …R_SRC_APRTR4__BASE_ADDR__SHIFT 0x0
42 …RTR4__BASE_ADDR_MASK 0x7FFFFFFFL
[all …]
/linux/Documentation/trace/coresight/
H A Dpanic.rst130 #ETM trig out[0] trigger to Channel 0
131 echo 0 4 > channels/trigin_attach
135 #ETF Flush in trigger from Channel 0
136 echo 0 1 > channels/trigout_attach
141 #ETR Flush in from Channel 0
142 echo 0 1 > channels/trigout_attach
228 a90153f3 stp x19, x20, [sp, #16]
232 900085b3 adrp x19, ffff800009b95000 <reserved_mem+0xc48>
234 910f4273 add x19, x19, #0x3d0
236 f8747a60 ldr x0, [x19, x20, lsl #3]
[all …]
/linux/drivers/scsi/aic7xxx/
H A Daic79xx_seq.h_shipped9 0xff, 0x02, 0x06, 0x78,
10 0x00, 0xea, 0x6e, 0x59,
11 0x01, 0xea, 0x04, 0x30,
12 0xff, 0x04, 0x0c, 0x78,
13 0x19, 0xea, 0x6e, 0x59,
14 0x19, 0xea, 0x04, 0x00,
15 0x33, 0xea, 0x68, 0x59,
16 0x33, 0xea, 0x00, 0x00,
17 0x60, 0x3a, 0x3a, 0x68,
18 0x04, 0x4d, 0x35, 0x78,
[all …]
/linux/sound/drivers/opl4/
H A Dyrw801.c40 snd_opl4_read_memory(opl4, buf, 0x001200, 15); in snd_yrw801_detect()
43 snd_opl4_read_memory(opl4, buf, 0x1ffffe, 2); in snd_yrw801_detect()
44 if (buf[0] != 0x01) in snd_yrw801_detect()
46 dev_dbg(opl4->card->dev, "YRW801 ROM version %02x.%02x\n", buf[0], buf[1]); in snd_yrw801_detect()
47 return 0; in snd_yrw801_detect()
58 {0x14, 0x27, {0x12c,7474,100, 0,0,0x00,0xc8,0x20,0xf2,0x13,0x08,0x0}},
59 {0x28, 0x2d, {0x12d,6816,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
60 {0x2e, 0x33, {0x12e,5899,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
61 {0x34, 0x39, {0x12f,5290,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
62 {0x3a, 0x3f, {0x130,4260,100, 0,0,0x0a,0xc8,0x20,0xf2,0x14,0x08,0x0}},
[all …]

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