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/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,q6asm.yaml39 #size-cells = <0>;
48 iommus = <&apps_smmu 0x1821 0x0>;
50 #size-cells = <0>;
53 dai@0 {
54 reg = <0>;
H A Dqcom,q6asm-dais.yaml32 const: 0
35 "^dai@[0-9]+$":
46 enum: [0, 1, 2]
49 - Q6ASM_DAI_TX_RX (0) for both tx and rx
78 iommus = <&apps_smmu 0x1821 0x0>;
80 #size-cells = <0>;
83 dai@0 {
84 reg = <0>;
/linux/drivers/net/wireless/broadcom/b43legacy/
H A Dilt.c23 0xFEB93FFD, 0xFEC63FFD, /* 0 */
24 0xFED23FFD, 0xFEDF3FFD,
25 0xFEEC3FFE, 0xFEF83FFE,
26 0xFF053FFE, 0xFF113FFE,
27 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
28 0xFF373FFF, 0xFF443FFF,
29 0xFF503FFF, 0xFF5D3FFF,
30 0xFF693FFF, 0xFF763FFF,
31 0xFF824000, 0xFF8F4000, /* 16 */
32 0xFF9B4000, 0xFFA84000,
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dtables.c21 0xFEB93FFD, 0xFEC63FFD, /* 0 */
22 0xFED23FFD, 0xFEDF3FFD,
23 0xFEEC3FFE, 0xFEF83FFE,
24 0xFF053FFE, 0xFF113FFE,
25 0xFF1E3FFE, 0xFF2A3FFF, /* 8 */
26 0xFF373FFF, 0xFF443FFF,
27 0xFF503FFF, 0xFF5D3FFF,
28 0xFF693FFF, 0xFF763FFF,
29 0xFF824000, 0xFF8F4000, /* 16 */
30 0xFF9B4000, 0xFFA84000,
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_tv.c16 #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on t…
17 #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */
67 #define FRAC_BITS 0xe
68 #define FRAC_MASK 0x3fff
87 0x0007,
88 0x003f,
89 0x0263,
90 0x0a24,
91 0x2a6b,
92 0x0a36,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_5_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_VERSION 0x000d
35 …e regSDMA0_UCODE_VERSION_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
[all …]
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
/linux/drivers/net/wireless/ath/wil6210/
H A Dwmi.h27 #define WMI_INVALID_TEMPERATURE (0xFFFFFFFF)
55 #define WMI_QOS_SET_VIF_PRIORITY (0xFF)
63 MID_DEFAULT = 0x00,
64 FIRST_DBG_MID_ID = 0x10,
65 LAST_DBG_MID_ID = 0xFE,
66 MID_BROADCAST = 0xFF,
74 WMI_FW_CAPABILITY_FTM = 0,
115 WMI_CONNECT_CMDID = 0x01,
116 WMI_DISCONNECT_CMDID = 0x03,
117 WMI_DISCONNECT_STA_CMDID = 0x04,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
/linux/drivers/pci/
H A Dquirks.c45 if (ret < 0) in pcie_lbms_seen()
48 return count > 0; in pcie_lbms_seen()
96 * Return 0 if the link has been successfully retrained. Return an error
102 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ in pcie_failed_link_retrain()
270 u8 cls = 0; in pci_apply_final_quirks()
304 return 0; in pci_apply_final_quirks()
342 pci_read_config_byte(d, 0x82, &dlc); in quirk_passive_release()
346 pci_write_config_byte(d, 0x82, dlc); in quirk_passive_release()
392 pci_read_config_dword(dev, 0x40, &pmbase); in quirk_tigerpoint_bm_sts()
393 pmbase = pmbase & 0xff80; in quirk_tigerpoint_bm_sts()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
[all …]