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/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,q6usb.yaml53 iommus = <&apps_smmu 0x180f 0x0>;
H A Dqcom,q6afe.yaml50 #size-cells = <0>;
65 #size-cells = <0>;
70 qcom,sd-lines = <0 1 2 3>;
77 iommus = <&apps_smmu 0x180f 0x0>;
/linux/drivers/tty/vt/
H A Ducs_width_table.h_shipped7 * Unicode Version: 16.0.0
12 { 0x00AD, 0x00AD }, /* SOFT HYPHEN */
13 { 0x0300, 0x036F }, /* COMBINING GRAVE ACCENT - COMBINING LATIN SMALL LETTER X */
14 { 0x0483, 0x0489 }, /* COMBINING CYRILLIC TITLO - COMBINING CYRILLIC MILLIONS SIGN */
15 { 0x0591, 0x05BD }, /* HEBREW ACCENT ETNAHTA - HEBREW POINT METEG */
16 { 0x05BF, 0x05BF }, /* HEBREW POINT RAFE */
17 { 0x05C1, 0x05C2 }, /* HEBREW POINT SHIN DOT - HEBREW POINT SIN DOT */
18 { 0x05C4, 0x05C5 }, /* HEBREW MARK UPPER DOT - HEBREW MARK LOWER DOT */
19 { 0x05C7, 0x05C7 }, /* HEBREW POINT QAMATS QATAN */
20 { 0x0600, 0x0605 }, /* ARABIC NUMBER SIGN - ARABIC NUMBER MARK ABOVE */
[all …]
/linux/drivers/net/dsa/microchip/
H A Dksz_common.c39 #define MIB_COUNTER_NUM 0x20
118 { 0x00, "rx" },
119 { 0x01, "rx_hi" },
120 { 0x02, "rx_undersize" },
121 { 0x03, "rx_fragments" },
122 { 0x04, "rx_oversize" },
123 { 0x05, "rx_jabbers" },
124 { 0x06, "rx_symbol_err" },
125 { 0x07, "rx_crc_err" },
126 { 0x08, "rx_align_err" },
[all …]
/linux/drivers/net/wireless/ath/wil6210/
H A Dwmi.h27 #define WMI_INVALID_TEMPERATURE (0xFFFFFFFF)
55 #define WMI_QOS_SET_VIF_PRIORITY (0xFF)
63 MID_DEFAULT = 0x00,
64 FIRST_DBG_MID_ID = 0x10,
65 LAST_DBG_MID_ID = 0xFE,
66 MID_BROADCAST = 0xFF,
74 WMI_FW_CAPABILITY_FTM = 0,
115 WMI_CONNECT_CMDID = 0x01,
116 WMI_DISCONNECT_CMDID = 0x03,
117 WMI_DISCONNECT_STA_CMDID = 0x04,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h27 // base address: 0x1300000
31 // base address: 0x1300000
35 // base address: 0x1300000
39 // base address: 0x1300000
43 // base address: 0x1300000
47 // base address: 0x1300020
51 // base address: 0x1300040
55 // base address: 0x1300060
59 // base address: 0x1300080
63 // base address: 0x13000a0
[all …]