/linux/lib/fonts/ |
H A D | font_sun8x16.c | 7 { 0, 0, FONTDATAMAX, 0 }, { 8 /* */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 9 /* */ 0x00,0x00,0x7e,0x81,0xa5,0x81,0x81,0xbd,0x99,0x81,0x81,0x7e,0x00,0x00,0x00,0x00, 10 /* */ 0x00,0x00,0x7e,0xff,0xdb,0xff,0xff,0xc3,0xe7,0xff,0xff,0x7e,0x00,0x00,0x00,0x00, 11 /* */ 0x00,0x00,0x00,0x00,0x6c,0xfe,0xfe,0xfe,0xfe,0x7c,0x38,0x10,0x00,0x00,0x00,0x00, 12 /* */ 0x00,0x00,0x00,0x00,0x10,0x38,0x7c,0xfe,0x7c,0x38,0x10,0x00,0x00,0x00,0x00,0x00, 13 /* */ 0x00,0x00,0x00,0x18,0x3c,0x3c,0xe7,0xe7,0xe7,0x18,0x18,0x3c,0x00,0x00,0x00,0x00, 14 /* */ 0x00,0x00,0x00,0x18,0x3c,0x7e,0xff,0xff,0x7e,0x18,0x18,0x3c,0x00,0x00,0x00,0x00, 15 /* */ 0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x3c,0x3c,0x18,0x00,0x00,0x00,0x00,0x00,0x00, 16 /* */ 0xff,0xff,0xff,0xff,0xff,0xff,0xe7,0xc3,0xc3,0xe7,0xff,0xff,0xff,0xff,0xff,0xff, [all …]
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H A D | font_acorn_8x8.c | 9 { 0, 0, FONTDATAMAX, 0 }, { 10 /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ^@ */ 11 /* 01 */ 0x7e, 0x81, 0xa5, 0x81, 0xbd, 0x99, 0x81, 0x7e, /* ^A */ 12 /* 02 */ 0x7e, 0xff, 0xbd, 0xff, 0xc3, 0xe7, 0xff, 0x7e, /* ^B */ 13 /* 03 */ 0x6c, 0xfe, 0xfe, 0xfe, 0x7c, 0x38, 0x10, 0x00, /* ^C */ 14 /* 04 */ 0x10, 0x38, 0x7c, 0xfe, 0x7c, 0x38, 0x10, 0x00, /* ^D */ 15 /* 05 */ 0x00, 0x18, 0x3c, 0xe7, 0xe7, 0x3c, 0x18, 0x00, /* ^E */ 16 /* 06 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, 17 /* 07 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, 18 /* 08 */ 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, [all …]
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H A D | font_pearl_8x8.c | 18 { 0, 0, FONTDATAMAX, 0 }, { 19 /* 0 0x00 '^@' */ 20 0x00, /* 00000000 */ 21 0x00, /* 00000000 */ 22 0x00, /* 00000000 */ 23 0x00, /* 00000000 */ 24 0x00, /* 00000000 */ 25 0x00, /* 00000000 */ 26 0x00, /* 00000000 */ 27 0x00, /* 00000000 */ [all …]
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H A D | font_8x8.c | 13 { 0, 0, FONTDATAMAX, 0 }, { 14 /* 0 0x00 '^@' */ 15 0x00, /* 00000000 */ 16 0x00, /* 00000000 */ 17 0x00, /* 00000000 */ 18 0x00, /* 00000000 */ 19 0x00, /* 00000000 */ 20 0x00, /* 00000000 */ 21 0x00, /* 00000000 */ 22 0x00, /* 00000000 */ [all …]
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H A D | font_8x16.c | 14 { 0, 0, FONTDATAMAX, 0 }, { 15 /* 0 0x00 '^@' */ 16 0x00, /* 00000000 */ 17 0x00, /* 00000000 */ 18 0x00, /* 00000000 */ 19 0x00, /* 00000000 */ 20 0x00, /* 00000000 */ 21 0x00, /* 00000000 */ 22 0x00, /* 00000000 */ 23 0x00, /* 00000000 */ [all …]
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/linux/drivers/media/usb/gspca/ |
H A D | dtcs033.c | 32 if (gspca_dev->usb_err < 0) in reg_rw() 36 usb_rcvctrlpipe(udev, 0), in reg_rw() 42 if (ret < 0) { in reg_rw() 53 int i = 0; in reg_reqs() 56 while ((i < n_reqs) && (gspca_dev->usb_err >= 0)) { in reg_reqs() 63 if (gspca_dev->usb_err < 0) { in reg_reqs() 111 return 0; in sd_config() 117 return 0; in sd_init() 137 gspca_frame_add(gspca_dev, FIRST_PACKET, NULL, 0); in dtcs033_pkt_scan() 141 gspca_frame_add(gspca_dev, LAST_PACKET, NULL, 0); in dtcs033_pkt_scan() [all …]
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/linux/drivers/gpu/drm/panel/ |
H A D | panel-himax-hx8394.c | 30 #define HX8394_CMD_SETSEQUENCE 0xb0 31 #define HX8394_CMD_SETPOWER 0xb1 32 #define HX8394_CMD_SETDISP 0xb2 33 #define HX8394_CMD_SETCYC 0xb4 34 #define HX8394_CMD_SETVCOM 0xb6 35 #define HX8394_CMD_SETTE 0xb7 36 #define HX8394_CMD_SETSENSOR 0xb8 37 #define HX8394_CMD_SETEXTC 0xb9 38 #define HX8394_CMD_SETMIPI 0xba 39 #define HX8394_CMD_SETOTP 0xbb [all …]
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H A D | panel-lincolntech-lcd197.c | 40 gpiod_set_value_cansleep(lcd->enable_gpio, 0); in lincoln_lcd197_panel_prepare() 42 if (err < 0) in lincoln_lcd197_panel_prepare() 49 gpiod_set_value_cansleep(lcd->reset_gpio, 0); in lincoln_lcd197_panel_prepare() 52 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb9, 0xff, 0x83, 0x99); in lincoln_lcd197_panel_prepare() 53 mipi_dsi_dcs_write_seq_multi(&ctx, 0xd2, 0x55); in lincoln_lcd197_panel_prepare() 54 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb1, 0x02, 0x04, 0x70, 0x90, 0x01, in lincoln_lcd197_panel_prepare() 55 0x32, 0x33, 0x11, 0x11, 0x4d, 0x57, 0x56, 0x73, in lincoln_lcd197_panel_prepare() 56 0x02, 0x02); in lincoln_lcd197_panel_prepare() 57 mipi_dsi_dcs_write_seq_multi(&ctx, 0xb2, 0x00, 0x80, 0x80, 0xae, 0x0a, in lincoln_lcd197_panel_prepare() 58 0x0e, 0x75, 0x11, 0x00, 0x00, 0x00); in lincoln_lcd197_panel_prepare() [all …]
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H A D | panel-himax-hx83102.c | 24 #define HX83102_SETPOWER 0xb1 25 #define HX83102_SETDISP 0xb2 26 #define HX83102_SETCYC 0xb4 27 #define HX83102_SETEXTC 0xb9 28 #define HX83102_SETMIPI 0xba 29 #define HX83102_SETVDC 0xbc 30 #define HX83102_SETBANK 0xbd 31 #define HX83102_UNKNOWN_BE 0xbe 32 #define HX83102_SETPTBA 0xbf 33 #define HX83102_SETSTBA 0xc0 [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_7_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]
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H A D | gmc_8_1_sh_mask.h | 27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]
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/linux/kernel/bpf/preload/iterators/ |
H A D | iterators.lskel-big-endian.h | 27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach() 29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach() 38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach() 40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach() 48 int ret = 0; in iterators_bpf__attach() 50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach() 51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach() 52 return ret < 0 ? ret : 0; in iterators_bpf__attach() 96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load() 97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load() [all …]
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H A D | iterators.lskel-little-endian.h | 27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach() 29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach() 38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach() 40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach() 48 int ret = 0; in iterators_bpf__attach() 50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach() 51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach() 52 return ret < 0 ? ret : 0; in iterators_bpf__attach() 96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load() 97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load() [all …]
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/linux/include/linux/mlx5/ |
H A D | mlx5_ifc.h | 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, [all …]
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H A D | mlx5_ifc_fpga.h | 36 u8 max_num_qps[0x10]; 37 u8 reserved_at_10[0x8]; 38 u8 total_rcv_credits[0x8]; 40 u8 reserved_at_20[0xe]; 41 u8 qp_type[0x2]; 42 u8 reserved_at_30[0x5]; 43 u8 rae[0x1]; 44 u8 rwe[0x1]; 45 u8 rre[0x1]; 46 u8 reserved_at_38[0x4]; [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/smu/ |
H A D | smu_7_0_0_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
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H A D | smu_7_1_2_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
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H A D | smu_7_1_3_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f 32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0 33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780 34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7 35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800 36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb [all …]
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H A D | smu_7_0_1_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
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H A D | smu_7_1_0_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
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H A D | smu_7_1_1_sh_mask.h | 27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
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/linux/sound/usb/usx2y/ |
H A D | usbusx2yaudio.c | 36 int i, len, lens = 0, hwptr_done = subs->hwptr_done; in usx2y_urb_capt_retire() 40 for (i = 0; i < nr_of_packs(); i++) { in usx2y_urb_capt_retire() 51 dev_dbg(&usx2y->dev->dev, "%s: 0 == len ERROR!\n", __func__); in usx2y_urb_capt_retire() 78 return 0; in usx2y_urb_capt_retire() 99 count = 0; in usx2y_urb_play_prepare() 100 for (pack = 0; pack < nr_of_packs(); pack++) { in usx2y_urb_play_prepare() 113 0; in usx2y_urb_play_prepare() 140 return 0; in usx2y_urb_play_prepare() 173 if (err < 0) { in usx2y_urb_submit() 178 return 0; in usx2y_urb_submit() [all …]
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/linux/arch/arm64/kvm/hyp/nvhe/ |
H A D | host.S | 27 stp x2, x3, [x0, #CPU_XREG_OFFSET(0)] 36 /* Store the host regs x18-x29, lr */ 49 add x18, x29, #CPU_APIAKEYLO_EL1 50 ptrauth_save_state x18, x19, x20 53 adr_this_cpu x18, kvm_hyp_ctxt, x19 54 add x18, x18, #CPU_APIAKEYLO_EL1 55 ptrauth_restore_state x18, x19, x20 71 add x18, x29, #CPU_APIAKEYLO_EL1 72 ptrauth_restore_state x18, x1 [all...] |
/linux/drivers/gpu/drm/amd/include/asic_reg/umc/ |
H A D | umc_6_7_0_sh_mask.h | 29 …C_UMC0_MCUMC_STATUST0__ErrorCode__SHIFT 0x0 30 …_UMC0_MCUMC_STATUST0__ErrorCodeExt__SHIFT 0x10 31 …_UMC0_MCUMC_STATUST0__RESERV22__SHIFT 0x16 32 …_UMC0_MCUMC_STATUST0__AddrLsb__SHIFT 0x18 33 …_UMC0_MCUMC_STATUST0__RESERV30__SHIFT 0x1e 34 …_UMC0_MCUMC_STATUST0__ErrCoreId__SHIFT 0x20 35 …_UMC0_MCUMC_STATUST0__RESERV38__SHIFT 0x26 36 …_UMC0_MCUMC_STATUST0__Scrub__SHIFT 0x28 37 …_UMC0_MCUMC_STATUST0__RESERV41__SHIFT 0x29 38 …_UMC0_MCUMC_STATUST0__Poison__SHIFT 0x2b [all …]
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | am335x-pocketbeagle.dts | 23 pinctrl-0 = <&usr_leds_pins>; 130 "[USR LED 0]", 151 "[SYSBOOT 0]", 220 /* P2_03 (ZCZ ball T10) gpio0_23 0x824 PIN 9 */ 225 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 226 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 229 /* P1_34 (ZCZ ball T11) gpio0_26 0x828 PIN 10 */ 234 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>; 235 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>; 238 /* P2_19 (ZCZ ball U12) gpio0_27 0x82c PIN 11 */ [all …]
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