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/linux/drivers/platform/x86/intel/pmc/
H A Dcore.h21 #define SLP_S0_RES_COUNTER_MASK GENMASK(31, 0)
23 #define PMC_BASE_ADDR_DEFAULT 0xFE000000
33 #define SPT_PMC_PCI_DEVICE_ID 0x9d21
34 #define SPT_PMC_BASE_ADDR_OFFSET 0x48
35 #define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET 0x13c
36 #define SPT_PMC_PM_CFG_OFFSET 0x18
37 #define SPT_PMC_PM_STS_OFFSET 0x1c
38 #define SPT_PMC_MTPMC_OFFSET 0x20
39 #define SPT_PMC_MFPMC_OFFSET 0x38
40 #define SPT_PMC_LTR_IGNORE_OFFSET 0x30C
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/linux/drivers/usb/host/
H A Dehci-pci.c22 #define PCI_DEVICE_ID_INTEL_CE4100_USB 0x2e70
24 #define PCI_VENDOR_ID_ASPEED 0x1a03
25 #define PCI_DEVICE_ID_ASPEED_EHCI 0x2603
28 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_SOC 0x0939
42 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0811), },
43 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0829), },
44 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xe006), },
54 * 0x84 is the offset of in/out threshold register,
59 /* Maximum usable threshold value is 0x7f dwords for both IN and OUT */
60 #define INTEL_QUARK_X1000_EHCI_MAX_THRESHOLD 0x007f007f
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H A Duhci-hcd.h10 #define PIPE_DEVEP_MASK 0x0007ff00
18 #define USBCMD 0
19 #define USBCMD_RS 0x0001 /* Run/Stop */
20 #define USBCMD_HCRESET 0x0002 /* Host reset */
21 #define USBCMD_GRESET 0x0004 /* Global reset */
22 #define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
23 #define USBCMD_FGR 0x0010 /* Force Global Resume */
24 #define USBCMD_SWDBG 0x0020 /* SW Debug mode */
25 #define USBCMD_CF 0x0040 /* Config Flag (sw only) */
26 #define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
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/linux/rust/kernel/pci/
H A Did.rs16 /// 23-16, subclass in bits 15-8, programming interface in bits 7-0).
41 Full = 0xffffff,
43 ClassSubclass = 0xffff00,
81 self.0 in as_raw()
90 if val > 0xFFFF { in to_24bit_class()
100 write!(f, "0x{:06x}", self.0) in fmt()
117 0xffffff => Ok(ClassMask::Full), in try_from()
118 0xffff00 => Ok(ClassMask::ClassSubclass), in try_from()
166 self.0 in as_raw()
173 write!(f, "0x{:04x}", self.0) in fmt()
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/linux/include/linux/
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x01060
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/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
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/linux/drivers/gpu/drm/radeon/
H A Dr600d.h30 #define CP_PACKET2 0x80000000
31 #define PACKET2_PAD_SHIFT 0
32 #define PACKET2_PAD_MASK (0x3fffffff << 0)
41 #define R6XX_MAX_BACKENDS_MASK 0xff
43 #define R6XX_MAX_SIMDS_MASK 0xff
45 #define R6XX_MAX_PIPES_MASK 0xff
48 #define ARRAY_LINEAR_GENERAL 0x00000000
49 #define ARRAY_LINEAR_ALIGNED 0x00000001
50 #define ARRAY_1D_TILED_THIN1 0x00000002
51 #define ARRAY_2D_TILED_THIN1 0x00000004
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/linux/sound/usb/
H A Dmixer_quirks.c84 cval->min = 0; in snd_create_std_mono_ctl_offset()
86 cval->res = 0; in snd_create_std_mono_ctl_offset()
87 cval->dBmin = 0; in snd_create_std_mono_ctl_offset()
88 cval->dBmax = 0; in snd_create_std_mono_ctl_offset()
104 kctl->vd[0].access |= in snd_create_std_mono_ctl_offset()
121 val_type, 0 /* Offset */, in snd_create_std_mono_ctl()
137 if (err < 0) in snd_create_std_mono_table()
142 return 0; in snd_create_std_mono_table()
189 { USB_ID(0x041e, 0x3000), 0, 1, 2, 1, 18, 0x0013 }, /* Extigy */
190 { USB_ID(0x041e, 0x3020), 2, 1, 6, 6, 18, 0x0013 }, /* Audigy 2 NX */
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/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x10A9
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x10B0
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
30 // base address: 0x4980
31 …SDMA0_DEC_START 0x0000
32 …ne mmSDMA0_DEC_START_BASE_IDX 0
33 …SDMA0_PG_CNTL 0x0016
34 …ne mmSDMA0_PG_CNTL_BASE_IDX 0
35 …SDMA0_PG_CTX_LO 0x0017
[all …]
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_12_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_MCU_MISC_CNTL 0x0001
33 …e regSDMA0_MCU_MISC_CNTL_BASE_IDX 0
34 …SDMA0_UCODE_REV 0x0003
35 …e regSDMA0_UCODE_REV_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x0005
37 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
38 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0006
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_10_3_0_offset.h25 …SQ_DEBUG_STS_GLOBAL 0x10A9
26 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
27 …SQ_DEBUG_STS_GLOBAL2 0x10B0
28 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
29 …SQ_DEBUG 0x10B1
30 …ne mmSQ_DEBUG_BASE_IDX 0
33 // base address: 0x4980
34 …SDMA0_DEC_START 0x0000
35 …ne mmSDMA0_DEC_START_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_4_1_0_offset.h11 // base address: 0x0
12 …DENTIST_DISPCLK_CNTL 0x0064
17 // base address: 0x0
18 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
20 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
22 …PHYPLLC_PIXCLK_RESYNC_CNTL 0x0042
24 …PHYPLLD_PIXCLK_RESYNC_CNTL 0x0043
26 …DP_DTO_DBUF_EN 0x0044
28 …DSCCLK3_DTO_PARAM 0x0045
30 …DSCCLK4_DTO_PARAM 0x0046
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_12_0_offset.h27 // base address: 0x48
28 …dispdec_VGA_MEM_WRITE_PAGE_ADDR 0x0012
29 …ne mmdispdec_VGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
33 // base address: 0x4c
34 …dispdec_VGA_MEM_READ_PAGE_ADDR 0x0014
35 …ne mmdispdec_VGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
39 // base address: 0x0
40 …DC_PERFMON0_PERFCOUNTER_CNTL 0x0020
42 …DC_PERFMON0_PERFCOUNTER_CNTL2 0x0021
44 …DC_PERFMON0_PERFCOUNTER_STATE 0x0022
[all …]