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/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Drpmh-rsc.txt52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
91 For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
92 register offsets for DRV2 start at 0D00, the register calculations are like
94 DRV0: 0x179C0000
95 DRV2: 0x179C0000 + 0x10000 = 0x179D0000
96 DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
97 TCS-OFFSET: 0xD00
102 reg = <0x179c0000 0x10000>,
103 <0x179d0000 0x10000>,
104 <0x179e0000 0x10000>;
[all …]
H A Dqcom,rpmh-rsc.yaml84 enum: [ 0, 1, 2, 3 ]
103 - const: drv-0
121 '^regulators(-[0-9])?$':
153 // For a TCS whose RSC base address is 0x179C0000 and is at a DRV id of
154 // 2, the register offsets for DRV2 start at 0D00, the register
156 // DRV0: 0x179C0000
157 // DRV2: 0x179C0000 + 0x10000 = 0x179D0000
158 // DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
159 // TCS-OFFSET: 0xD00
165 reg = <0x179c0000 0x10000>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm670.dtsi37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
82 reg = <0x0 0x100>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
104 reg = <0x0 0x200>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi79 #clock-cells = <0>;
86 #clock-cells = <0>;
93 #size-cells = <0>;
95 cpu0: cpu@0 {
98 reg = <0x0 0x0>;
99 clocks = <&cpufreq_hw 0>;
103 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0x0 0x100>;
128 clocks = <&cpufreq_hw 0>;
132 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]