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/linux/arch/arm/boot/dts/rockchip/
H A Drk3288-veyron-jerry.dts25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
45 #size-cells = <0>;
52 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
53 0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
54 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
55 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
56 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
57 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
58 0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
59 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dpm6150.dtsi22 hysteresis = <0>;
28 hysteresis = <0>;
37 pm6150_lsid0: pmic@0 {
39 reg = <0x0 SPMI_USID>;
41 #size-cells = <0>;
45 reg = <0x800>;
46 mode-bootloader = <0x2>;
47 mode-recovery = <0x1>;
51 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
59 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpm8150b.dtsi21 hysteresis = <0>;
27 hysteresis = <0>;
33 hysteresis = <0>;
44 reg = <0x2 SPMI_USID>;
46 #size-cells = <0>;
50 reg = <0x0800>;
58 reg = <0x1100>;
64 reg = <0x1500>,
65 <0x1700>;
66 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
[all …]
H A Dpm7250b.dtsi20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
45 #size-cells = <0>;
49 reg = <0x1100>;
55 reg = <0x1500>,
56 <0x1700>;
57 interrupts = <PM7250B_SID 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
58 <PM7250B_SID 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
59 <PM7250B_SID 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
[all …]
/linux/drivers/net/ieee802154/
H A Dat86rf230.h15 #define RG_TRX_STATUS (0x01)
16 #define SR_TRX_STATUS 0x01, 0x1f, 0
17 #define SR_RESERVED_01_3 0x01, 0x20, 5
18 #define SR_CCA_STATUS 0x01, 0x40, 6
19 #define SR_CCA_DONE 0x01, 0x80, 7
20 #define RG_TRX_STATE (0x02)
21 #define SR_TRX_CMD 0x02, 0x1f, 0
22 #define SR_TRAC_STATUS 0x02, 0xe0, 5
23 #define RG_TRX_CTRL_0 (0x03)
24 #define SR_CLKM_CTRL 0x03, 0x07, 0
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2059.c17 { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 },
18 { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 },
19 { 0x188, 0x05 },
61 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
62 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
63 0x00, 0x00, 0x00, 0xd0, 0x00),
64 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
68 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
69 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
70 0x00, 0x00, 0x00, 0xd0, 0x00),
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-raydium-rm67191.c25 #define COL_FMT_16BPP 0x55
26 #define COL_FMT_18BPP 0x66
27 #define COL_FMT_24BPP 0x77
30 #define WRMAUCCTR 0xFE
43 {0xFE, 0x0B},
44 {0x28, 0x40},
45 {0x29, 0x4F},
46 {0xFE, 0x0E},
47 {0x4B, 0x00},
48 {0x4C, 0x0F},
[all …]
H A Dpanel-jadard-jd9365da-h3.c48 #define JD9365DA_DCS_SWITCH_PAGE 0xe0
55 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe1, 0x93); in jadard_enable_standard_cmds()
56 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe2, 0x65); in jadard_enable_standard_cmds()
57 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xe3, 0xf8); in jadard_enable_standard_cmds()
58 mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x03); in jadard_enable_standard_cmds()
112 gpiod_set_value(jadard->reset, 0); in jadard_prepare()
118 gpiod_set_value(jadard->reset, 0); in jadard_prepare()
125 return 0; in jadard_prepare()
136 gpiod_set_value(jadard->reset, 0); in jadard_unprepare()
144 return 0; in jadard_unprepare()
[all …]
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)
100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
[all …]
/linux/lib/crypto/
H A Dcurve25519-fiat32.c18 * entries t[0]...t[9], represents the integer t[0]+2^26 t[1]+2^51 t[2]+2^77
41 h[0] = a0&((1<<26)-1); /* 26 used, 32-26 left. 26 */ in fe_frombytes_impl()
104 t = -!!t; /* all set if nonzero, 0 if 0 */ in cmovznz32()
110 { const u32 x17 = in1[9]; in fe_freeze() local
119 { const u32 x2 = in1[0]; in fe_freeze()
120 { u32 x20; u8/*bool*/ x21 = subborrow_u26(0x0, x2, 0x3ffffed, &x20); in fe_freeze()
121 { u32 x23; u8/*bool*/ x24 = subborrow_u25(x21, x4, 0x1ffffff, &x23); in fe_freeze()
122 { u32 x26; u8/*bool*/ x27 = subborrow_u26(x24, x6, 0x3ffffff, &x26); in fe_freeze()
123 { u32 x29; u8/*bool*/ x30 = subborrow_u25(x27, x8, 0x1ffffff, &x29); in fe_freeze()
124 { u32 x32; u8/*bool*/ x33 = subborrow_u26(x30, x10, 0x3ffffff, &x32); in fe_freeze()
[all …]
H A Daescfb.c48 while (len > 0) { in aescfb_encrypt()
76 aescfb_encrypt_block(ctx, ks[0], iv); in aescfb_decrypt()
78 for (int i = 0; len > 0; i ^= 1) { in aescfb_decrypt()
125 "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
130 "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17"
149 "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
154 "\xf6\x9f\x24\x45\xdf\x4f\x9b\x17"
158 "\x67\xce\x7f\x7f\x81\x17\x36\x21"
159 "\x96\x1a\x2b\x70\x17\x1d\x3d\x7a"
174 "\xe9\x3d\x7e\x11\x73\x93\x17\x2a"
[all …]
/linux/drivers/mtd/spi-nor/
H A Deon.c13 .id = SNOR_ID(0x1c, 0x20, 0x16),
17 .id = SNOR_ID(0x1c, 0x20, 0x17),
21 .id = SNOR_ID(0x1c, 0x30, 0x14),
26 .id = SNOR_ID(0x1c, 0x30, 0x16),
30 .id = SNOR_ID(0x1c, 0x30, 0x17),
35 .id = SNOR_ID(0x1c, 0x31, 0x16),
41 .id = SNOR_ID(0x1c, 0x38, 0x17),
45 .id = SNOR_ID(0x1c, 0x70, 0x15),
50 .id = SNOR_ID(0x1c, 0x70, 0x16),
54 .id = SNOR_ID(0x1c, 0x70, 0x17),
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_sh_mask.h29 …NTL__READ_TIMEOUT__SHIFT 0x0
30 …TL__REPORT_LAST_RDERR__SHIFT 0x1f
31 …D_TIMEOUT_MASK 0x000000FFL
32 …ORT_LAST_RDERR_MASK 0x80000000L
34 …KEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
35 …KEW_CNTL__SKEW_COUNT__SHIFT 0x6
36 …__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
37 …__SKEW_COUNT_MASK 0x00000FC0L
39 …TATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
40 …TATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
[all …]
H A Dgc_9_0_sh_mask.h25 …DC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0
26 …DC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2
27 …DC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4
28 …DC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6
29 …DC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8
30 …DC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa
31 …DC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc
32 …DC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe
33 …C_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10
34 …C_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12
[all …]
H A Dgc_9_1_sh_mask.h27 …NTL__READ_TIMEOUT__SHIFT 0x0
28 …TL__REPORT_LAST_RDERR__SHIFT 0x1f
29 …D_TIMEOUT_MASK 0x000000FFL
30 …ORT_LAST_RDERR_MASK 0x80000000L
32 …KEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
33 …KEW_CNTL__SKEW_COUNT__SHIFT 0x6
34 …__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
35 …__SKEW_COUNT_MASK 0x00000FC0L
37 …TATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
38 …TATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
[all …]
H A Dgc_9_2_1_sh_mask.h27 …NTL__READ_TIMEOUT__SHIFT 0x0
28 …TL__REPORT_LAST_RDERR__SHIFT 0x1f
29 …D_TIMEOUT_MASK 0x000000FFL
30 …ORT_LAST_RDERR_MASK 0x80000000L
32 …KEW_CNTL__SKEW_TOP_THRESHOLD__SHIFT 0x0
33 …KEW_CNTL__SKEW_COUNT__SHIFT 0x6
34 …__SKEW_TOP_THRESHOLD_MASK 0x0000003FL
35 …__SKEW_COUNT_MASK 0x00000FC0L
37 …TATUS2__ME0PIPE1_CMDFIFO_AVAIL__SHIFT 0x0
38 …TATUS2__ME0PIPE1_CF_RQ_PENDING__SHIFT 0x4
[all …]
/linux/drivers/media/dvb-frontends/
H A Ditd1000.c31 } while (0)
35 } while (0)
39 } while (0)
46 .addr = state->cfg->i2c_address, .flags = 0, .buf = buf, .len = len+1 in itd1000_write_regs()
56 buf[0] = reg; in itd1000_write_regs()
59 /* itd_dbg("wr %02x: %02x\n", reg, v[0]); */ in itd1000_write_regs()
65 return 0; in itd1000_write_regs()
72 { .addr = state->cfg->i2c_address, .flags = 0, .buf = &reg, .len = 1 }, in itd1000_read_reg()
77 itd1000_write_regs(state, (reg - 1) & 0xff, &state->shadow[(reg - 1) & 0xff], 1); in itd1000_read_reg()
100 { 0, 0x8, 0x3 },
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_7_2_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE_MASK 0x8
36 #define CB_COLOR_CONTROL__DEGAMMA_ENABLE__SHIFT 0x3
[all …]
/linux/drivers/gpu/drm/amd/include/ivsrcid/
H A Divsrcid_vislands30.h30 #define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07
31 #define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0
33 #define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08
34 #define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0
36 #define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09
37 #define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0
39 #define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a
40 #define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0
42 #define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b
43 #define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0
[all …]
/linux/drivers/net/wireless/realtek/rtl818x/rtl8180/
H A Drtl8225se.c24 0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
25 0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
26 0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
27 0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
28 0x0183, 0x0163, 0x0143, 0x0123, 0x0103
32 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
33 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
34 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
35 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
36 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
[all …]
/linux/drivers/scsi/
H A Datp870u.c133 for (c = 0; c < 2; c++) { in atp870u_intr_handle()
134 j = atp_readb_io(dev, c, 0x1f); in atp870u_intr_handle()
135 if ((j & 0x80) != 0) in atp870u_intr_handle()
137 dev->in_int[c] = 0; in atp870u_intr_handle()
139 if ((j & 0x80) == 0) in atp870u_intr_handle()
145 cmdp = atp_readb_io(dev, c, 0x10); in atp870u_intr_handle()
146 if (dev->working[c] != 0) { in atp870u_intr_handle()
148 if ((atp_readb_io(dev, c, 0x16) & 0x80) == 0) in atp870u_intr_handle()
149 atp_writeb_io(dev, c, 0x16, in atp870u_intr_handle()
150 (atp_readb_io(dev, c, 0x16) | 0x80)); in atp870u_intr_handle()
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4fw_version.h38 #define T4FW_VERSION_MAJOR 0x01
39 #define T4FW_VERSION_MINOR 0x17
40 #define T4FW_VERSION_MICRO 0x03
41 #define T4FW_VERSION_BUILD 0x00
43 #define T4FW_MIN_VERSION_MAJOR 0x01
44 #define T4FW_MIN_VERSION_MINOR 0x04
45 #define T4FW_MIN_VERSION_MICRO 0x00
47 #define T5FW_VERSION_MAJOR 0x01
48 #define T5FW_VERSION_MINOR 0x17
49 #define T5FW_VERSION_MICRO 0x03
[all …]
/linux/arch/arm64/kernel/
H A Dsmccc-call.S12 \instr #0
54 /* Load the registers x0 - x17 from the struct arm_smccc_1_2_regs */
63 ldp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]
65 \instr #0
70 /* Store the registers x0 - x17 into the result structure */
79 stp x16, x17, [x19, #ARM_SMCCC_1_2_REGS_X16_OFFS]

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