/freebsd/sys/contrib/device-tree/Bindings/leds/ |
H A D | leds-bcm6358.txt | 4 In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller), 5 which can either be controlled by software (exporting the 74x164 as spi-gpio. 12 - #size-cells : must be 0. 24 - reg : LED pin number (only LEDs 0 to 31 are valid). 38 #size-cells = <0>; 39 reg = <0xfffe00d0 0x8>; 42 reg = <0>; 67 #size-cells = <0>; 68 reg = <0x100000d0 0x8>; 73 reg = <0>;
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H A D | leds-bcm6328.txt | 5 However, on some devices there are Serial LEDs (LEDs connected to a 74x164 6 controller), which can either be controlled by software (exporting the 74x164 10 exporting the 74x164 as spi-gpio prevents those LEDs to be hardware 15 with 0 meaning hardware control enabled and 1 hardware control disabled. This 26 - #size-cells : must be 0. 44 - reg : LED pin number (only LEDs 0 to 23 are valid). 61 these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may 62 be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs 67 these LEDs. Only valid for LEDs 0 to 7, where LED signals 0 to 3 may 68 be muxed to LEDs 0 to 3, and signals 4 to 7 may be muxed to LEDs [all …]
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H A D | leds-bcm6328.yaml | 15 However, on some devices there are Serial LEDs (LEDs connected to a 74x164 16 controller), which can either be controlled by software (exporting the 74x164 21 exporting the 74x164 as spi-gpio prevents those LEDs to be hardware 26 with 0 meaning hardware control enabled and 1 hardware control disabled. This 67 const: 0 79 description: LED pin number (only LEDs 0 to 23 are valid). 91 signals can get muxed into these LEDs. Only valid for LEDs 0 to 7, 92 where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and signals 4 to 102 hardware signals can get muxed into these LEDs. Only valid for LEDs 0 103 to 7, where LED signals 0 to 3 may be muxed to LEDs 0 to 3, and [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
H A D | dm814.h | 8 #define DM814_CLKCTRL_OFFSET 0x0 12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58) 15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150) 16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154) 17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158) 18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c) 19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160) 20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164) 21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168) 22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c) [all …]
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H A D | dm816.h | 8 #define DM816_CLKCTRL_OFFSET 0x0 12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58) 15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150) 16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154) 17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158) 18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c) 19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160) 20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164) 21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168) 22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170) [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx6dl-pinfunc.h | 13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 [all …]
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H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imx51-pinfunc.h | 13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 [all …]
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H A D | imx35-pinfunc.h | 13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 [all …]
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/freebsd/contrib/netbsd-tests/lib/libcurses/tests/ |
H A D | std_defines | 8 assign TRUE 0x01 9 assign FALSE 0x00 13 assign COLOR_BLACK 0x00 14 assign COLOR_RED 0x01 15 assign COLOR_GREEN 0x02 16 assign COLOR_YELLOW 0x03 17 assign COLOR_BLUE 0x04 18 assign COLOR_MAGENTA 0x05 19 assign COLOR_CYAN 0x06 20 assign COLOR_WHITE 0x07 [all …]
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/freebsd/sys/contrib/device-tree/Bindings/mfd/ |
H A D | brcm,cru.yaml | 61 reg = <0x1800c100 0x1d0>; 69 reg = <0x100 0x14>; 77 reg = <0x140 0x24>; 85 reg = <0x164 0x4>; 89 #phy-cells = <0>; 94 reg = <0x180 0x4>; 99 reg = <0x1c0 0x24>; 105 reg = <0x2c0 0x10>; 106 #thermal-sensor-cells = <0>;
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/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/ |
H A D | vf610-pinfunc.h | 14 #define ALT0 0x0 15 #define ALT1 0x1 16 #define ALT2 0x2 17 #define ALT3 0x3 18 #define ALT4 0x4 19 #define ALT5 0x5 20 #define ALT6 0x6 21 #define ALT7 0x7 24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0 25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0 [all …]
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/freebsd/sys/dev/xilinx/ |
H A D | xlnx_pcib.h | 36 #define XLNX_PCIE_VSEC 0x12c 37 #define XLNX_PCIE_BIR 0x130 /* Bridge Info Register */ 38 #define XLNX_PCIE_BSCR 0x134 /* Bridge Status and Control */ 39 #define XLNX_PCIE_IDR 0x138 /* Interrupt Decode Register */ 40 #define XLNX_PCIE_IMR 0x13C /* Interrupt Mask Register */ 41 #define IMR_LINK_DOWN (1 << 0) 44 #define IMR_CFG_COMPL_STATUS_M (0x7 << IMR_CFG_COMPL_STATUS_S) 59 #define XLNX_PCIE_BLR 0x140 /* Bus Location Register */ 60 #define XLNX_PCIE_PHYSCR 0x144 /* PHY Status/Control Register */ 62 #define XLNX_PCIE_RPSCR 0x148 /* Root Port Status/Control Register */ [all …]
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/freebsd/sys/arm/freescale/imx/ |
H A D | imx6_anatopreg.h | 32 #define IMX6_ANALOG_CCM_PLL_ARM 0x000 33 #define IMX6_ANALOG_CCM_PLL_ARM_SET 0x004 34 #define IMX6_ANALOG_CCM_PLL_ARM_CLR 0x008 35 #define IMX6_ANALOG_CCM_PLL_ARM_TOG 0x00C 36 #define IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK 0x7F 39 #define IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK (0x03 << 16) 40 #define IMX6_ANALOG_CCM_PLL_USB1 0x010 41 #define IMX6_ANALOG_CCM_PLL_USB1_SET 0x014 42 #define IMX6_ANALOG_CCM_PLL_USB1_CLR 0x018 43 #define IMX6_ANALOG_CCM_PLL_USB1_TOG 0x01C [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | nvidia,tegra124-pinmux.txt | 118 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 119 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 120 <0x0 0x70000820 0x0 0x8>; /* MIPI pad control */ 152 pinctrl-0 = <&sdmmc4_default>;
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H A D | nvidia,tegra124-pinmux.yaml | 147 reg = <0x70000868 0x164>, /* Pad control registers */ 148 <0x70003000 0x434>, /* Mux registers */ 149 <0x70000820 0x8>; /* MIPI pad control */
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/freebsd/sys/dev/bhnd/cores/pcie2/ |
H A D | bhnd_pcie2_reg.h | 31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */ 32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */ 38 #define BHND_PCIE2_CLK_CONTROL 0x000 40 #define BHND_PCIE2_RC_PM_CONTROL 0x004 41 #define BHND_PCIE2_RC_PM_STATUS 0x008 42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C 43 #define BHND_PCIE2_EP_PM_STATUS 0x010 44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014 45 #define BHND_PCIE2_EP_LTR_STATUS 0x018 46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C [all …]
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | omap4-var-om44customboard.dtsi | 16 pinctrl-0 = <&gpio_led_pins>; 33 pinctrl-0 = <&gpio_key_pins>; 35 #size-cells = <0>; 48 pinctrl-0 = <&hdmi_hpd_pins>; 65 OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1) /* mcspi1_cs2.uart1_cts */ 66 OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1) /* mcspi1_cs3.uart1_rts */ 67 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1) /* i2c2_scl.uart1_rx */ 68 OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1) /* i2c2_sda.uart1_tx */ 74 OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ 75 OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm/intel/ixp/ |
H A D | intel-ixp42x-goramo-multilink.dts | 25 memory@0 { 31 reg = <0x00000000 0x4000000>; 49 * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different) 53 cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 68 flash@0,0 { 74 reg = <0 0x00000000 0x100000 [all...] |