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/linux/Documentation/devicetree/bindings/media/
H A Dmediatek,vcodec-decoder.yaml151 reg = <0x16020000 0x1000>, /*VDEC_MISC*/
152 <0x16021000 0x800>, /*VDEC_LD*/
153 <0x16021800 0x800>, /*VDEC_TOP*/
154 <0x16022000 0x1000>, /*VDEC_CM*/
155 <0x16023000 0x1000>, /*VDEC_AD*/
156 <0x16024000 0x1000>, /*VDEC_AV*/
157 <0x16025000 0x1000>, /*VDEC_PP*/
158 <0x16026800 0x800>, /*VP8_VD*/
159 <0x16027000 0x800>, /*VP6_VD*/
160 <0x16027800 0x800>, /*VP8_VL*/
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-shx3.c20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi20 #size-cells = <0>;
22 S7_0: cpu@0 {
24 reg = <0>;
200 cpu_opp: opp-table-0 {
260 #clock-cells = <0>;
265 #clock-cells = <0>;
271 #clock-cells = <0>;
277 #clock-cells = <0>;
283 #clock-cells = <0>;
289 #clock-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]
H A Dmt8183.dtsi293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
[all …]