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/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2057.c17 { 0x0E, 0x20 }, { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 },
18 { 0x35, 0x26 }, { 0x3C, 0xff }, { 0x3D, 0xff }, { 0x3E, 0xff },
19 { 0x3F, 0xff }, { 0x62, 0x33 }, { 0x8A, 0xf0 }, { 0x8B, 0x10 },
20 { 0x8C, 0xf0 }, { 0x91, 0x3f }, { 0x92, 0x36 }, { 0xA4, 0x8c },
21 { 0xA8, 0x55 }, { 0xAF, 0x01 }, { 0x10F, 0xf0 }, { 0x110, 0x10 },
22 { 0x111, 0xf0 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x129, 0x8c },
23 { 0x12D, 0x55 }, { 0x134, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 },
24 { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 },
25 { 0x169, 0x02 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 },
26 { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 },
[all …]
H A Dradio_2059.c17 { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 },
18 { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 },
19 { 0x188, 0x05 },
61 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
62 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
63 0x00, 0x00, 0x00, 0xd0, 0x00),
64 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
68 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
69 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
70 0x00, 0x00, 0x00, 0xd0, 0x00),
[all …]
/linux/arch/arm/mach-omap2/
H A Dopp4xxx_data.c32 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
33 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
34 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
35 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
36 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITROSB_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB, 0xfa, 0x27),
37 VOLT_DATA_DEFINE(0, 0, 0, 0),
45 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
46 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16),
47 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23),
48 VOLT_DATA_DEFINE(0, 0, 0, 0),
[all …]
/linux/kernel/bpf/preload/iterators/
H A Diterators.lskel-big-endian.h27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach()
29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach()
38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach()
40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach()
48 int ret = 0; in iterators_bpf__attach()
50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach()
51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach()
52 return ret < 0 ? ret : 0; in iterators_bpf__attach()
93 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
94 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load()
[all …]
/linux/arch/arm64/include/asm/
H A Dmodule.h35 * (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or
38 * is exactly what we are dealing with here, we are free to use x16
41 __le32 adrp; /* adrp x16, .... */
42 __le32 add; /* add x16, x16, #0x.... */
43 __le32 br; /* br x16 */
49 ((u64)place & 0xfff) >= 0xff8; in is_forbidden_offset_for_adrp()
62 if (strcmp(name, secstrs + s->sh_name) == 0) in find_section()
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-phyboard-polis-peb-eval-01.dtso17 pinctrl-0 = <&pinctrl_gpio_keys>;
19 button-0 {
37 pinctrl-0 = <&pinctrl_user_leds>;
59 MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x16
60 MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
66 MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x16
67 MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
68 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x16
H A Dimx8mp-icore-mx8mp-edimm2.2.dts28 pinctrl-0 = <&pinctrl_reg_usb1>;
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
49 pinctrl-0 = <&pinctrl_eqos>;
57 #size-cells = <0>;
61 micrel,led-mode = <0>;
70 pinctrl-0 = <&pinctrl_uart2>;
105 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
113 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
114 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
115 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_0_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_2_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_4_1_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_3_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_9_1_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_1_8_0_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_1_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_3_0_1_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_1_7_sh_mask.h29 …RDCLI0__VIRT_CHAN__SHIFT 0x0
30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
31 …RDCLI0__URG_HIGH__SHIFT 0x4
32 …RDCLI0__URG_LOW__SHIFT 0x8
33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
34 …RDCLI0__MAX_BW__SHIFT 0xd
35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
36 …DCLI0__MIN_BW__SHIFT 0x16
37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
38 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_9_3_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_2_0_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
H A Dmmhub_2_3_0_sh_mask.h27 …RDCLI0__VIRT_CHAN__SHIFT 0x0
28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3
29 …RDCLI0__URG_HIGH__SHIFT 0x4
30 …RDCLI0__URG_LOW__SHIFT 0x8
31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc
32 …RDCLI0__MAX_BW__SHIFT 0xd
33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15
34 …DCLI0__MIN_BW__SHIFT 0x16
35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19
36 …DCLI0__MAX_OSD__SHIFT 0x1a
[all …]
/linux/arch/arm64/kernel/
H A Defi-rt-wrapper.S32 ldr_l x16, efi_rt_stack_top
33 mov sp, x16
49 mov x16, sp
51 str xzr, [x16, #8] // clear recorded task SP value
56 b.ne 0f
58 0:
77 ldr_l x16, efi_rt_stack_top // clear recorded task SP value
78 str xzr, [x16, #-8]
/linux/drivers/media/dvb-frontends/
H A Drtl2832_priv.h242 {DVBT_DAGC_TRG_VAL, 0x39},
243 {DVBT_AGC_TARG_VAL_0, 0x0},
244 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
245 {DVBT_AAGC_LOOP_GAIN, 0x16},
246 {DVBT_LOOP_GAIN2_3_0, 0x6},
247 {DVBT_LOOP_GAIN2_4, 0x1},
248 {DVBT_LOOP_GAIN3, 0x16},
249 {DVBT_VTOP1, 0x35},
250 {DVBT_VTOP2, 0x21},
251 {DVBT_VTOP3, 0x21},
[all …]
/linux/drivers/phy/starfive/
H A Dphy-jh7110-dphy-tx.c26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
27 #define STF_DPHY_AON_POWER_READY_N BIT(0)
43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0)
45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0)
47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0)
54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0)
59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0)
64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0)
65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0)
100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d},
[all …]
/linux/drivers/mtd/spi-nor/
H A Deon.c13 .id = SNOR_ID(0x1c, 0x20, 0x16),
17 .id = SNOR_ID(0x1c, 0x20, 0x17),
21 .id = SNOR_ID(0x1c, 0x30, 0x14),
26 .id = SNOR_ID(0x1c, 0x30, 0x16),
30 .id = SNOR_ID(0x1c, 0x30, 0x17),
35 .id = SNOR_ID(0x1c, 0x31, 0x16),
41 .id = SNOR_ID(0x1c, 0x38, 0x17),
45 .id = SNOR_ID(0x1c, 0x70, 0x15),
50 .id = SNOR_ID(0x1c, 0x70, 0x16),
54 .id = SNOR_ID(0x1c, 0x70, 0x17),
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_sh_mask.h26 …C_TAG_CNT__DED_COUNT__SHIFT 0x0
27 …C_TAG_CNT__SEC_COUNT__SHIFT 0x2
28 …T__DED_COUNT_MASK 0x00000003L
29 …T__SEC_COUNT_MASK 0x0000000CL
31 …C_ROQ_CNT__DED_COUNT_ME1__SHIFT 0x0
32 …C_ROQ_CNT__SEC_COUNT_ME1__SHIFT 0x2
33 …C_ROQ_CNT__DED_COUNT_ME2__SHIFT 0x4
34 …C_ROQ_CNT__SEC_COUNT_ME2__SHIFT 0x6
35 …T__DED_COUNT_ME1_MASK 0x00000003L
36 …T__SEC_COUNT_ME1_MASK 0x0000000CL
[all …]
/linux/drivers/gpu/drm/amd/include/ivsrcid/
H A Divsrcid_vislands30.h30 #define VISLANDS30_IV_SRCID_D1_V_UPDATE_INT 7 // 0x07
31 #define VISLANDS30_IV_EXTID_D1_V_UPDATE_INT 0
33 #define VISLANDS30_IV_SRCID_D1_GRPH_PFLIP 8 // 0x08
34 #define VISLANDS30_IV_EXTID_D1_GRPH_PFLIP 0
36 #define VISLANDS30_IV_SRCID_D2_V_UPDATE_INT 9 // 0x09
37 #define VISLANDS30_IV_EXTID_D2_V_UPDATE_INT 0
39 #define VISLANDS30_IV_SRCID_D2_GRPH_PFLIP 10 // 0x0a
40 #define VISLANDS30_IV_EXTID_D2_GRPH_PFLIP 0
42 #define VISLANDS30_IV_SRCID_D3_V_UPDATE_INT 11 // 0x0b
43 #define VISLANDS30_IV_EXTID_D3_V_UPDATE_INT 0
[all …]

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