/linux/kernel/bpf/preload/iterators/ |
H A D | iterators.lskel-big-endian.h | 27 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_map__attach() 29 if (fd > 0) in iterators_bpf__dump_bpf_map__attach() 38 int fd = skel_link_create(prog_fd, 0, BPF_TRACE_ITER); in iterators_bpf__dump_bpf_prog__attach() 40 if (fd > 0) in iterators_bpf__dump_bpf_prog__attach() 48 int ret = 0; in iterators_bpf__attach() 50 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_map__attach(skel); in iterators_bpf__attach() 51 ret = ret < 0 ? ret : iterators_bpf__dump_bpf_prog__attach(skel); in iterators_bpf__attach() 52 return ret < 0 ? ret : 0; in iterators_bpf__attach() 96 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load() 97 \0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\ in iterators_bpf__load() [all …]
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/linux/drivers/net/wireless/broadcom/b43/ |
H A D | radio_2057.c | 17 { 0x0E, 0x20 }, { 0x31, 0x00 }, { 0x32, 0x00 }, { 0x33, 0x00 }, 18 { 0x35, 0x26 }, { 0x3C, 0xff }, { 0x3D, 0xff }, { 0x3E, 0xff }, 19 { 0x3F, 0xff }, { 0x62, 0x33 }, { 0x8A, 0xf0 }, { 0x8B, 0x10 }, 20 { 0x8C, 0xf0 }, { 0x91, 0x3f }, { 0x92, 0x36 }, { 0xA4, 0x8c }, 21 { 0xA8, 0x55 }, { 0xAF, 0x01 }, { 0x10F, 0xf0 }, { 0x110, 0x10 }, 22 { 0x111, 0xf0 }, { 0x116, 0x3f }, { 0x117, 0x36 }, { 0x129, 0x8c }, 23 { 0x12D, 0x55 }, { 0x134, 0x01 }, { 0x15E, 0x00 }, { 0x15F, 0x00 }, 24 { 0x160, 0x00 }, { 0x161, 0x00 }, { 0x162, 0x00 }, { 0x163, 0x00 }, 25 { 0x169, 0x02 }, { 0x16A, 0x00 }, { 0x16B, 0x00 }, { 0x16C, 0x00 }, 26 { 0x1A4, 0x00 }, { 0x1A5, 0x00 }, { 0x1A6, 0x00 }, { 0x1AA, 0x00 }, [all …]
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H A D | radio_2059.c | 17 { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 }, 18 { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 }, 19 { 0x188, 0x05 }, 61 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c, 62 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, 63 0x00, 0x00, 0x00, 0xd0, 0x00), 64 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443), 68 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71, 69 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73, 70 0x00, 0x00, 0x00, 0xd0, 0x00), [all …]
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/linux/arch/arm/mach-omap2/ |
H A D | opp4xxx_data.c | 32 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c), 33 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16), 34 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23), 35 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27), 36 VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITROSB_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB, 0xfa, 0x27), 37 VOLT_DATA_DEFINE(0, 0, 0, 0), 45 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c), 46 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP100_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP100, 0xf9, 0x16), 47 VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_IVA_OPPTURBO, 0xfa, 0x23), 48 VOLT_DATA_DEFINE(0, 0, 0, 0), [all …]
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/linux/arch/arm/boot/dts/rockchip/ |
H A D | rk3288-veyron-jerry.dts | 25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; 45 #size-cells = <0>; 52 0x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01 53 0x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 54 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 55 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f 56 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 57 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 58 0x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 59 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c [all …]
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/linux/arch/arm64/include/asm/ |
H A D | module.h | 34 * (AAPCS64) must assume that a veneer that alters IP0 (x16) and/or 37 * is exactly what we are dealing with here, we are free to use x16 40 __le32 adrp; /* adrp x16, .... */ 41 __le32 add; /* add x16, x16, #0x.... */ 42 __le32 br; /* br x16 */ 48 ((u64)place & 0xfff) >= 0xff8; in is_forbidden_offset_for_adrp() 61 if (strcmp(name, secstrs + s->sh_name) == 0) in find_section()
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/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mp-icore-mx8mp-edimm2.2.dts | 28 pinctrl-0 = <&pinctrl_reg_usb1>; 39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 49 pinctrl-0 = <&pinctrl_eqos>; 57 #size-cells = <0>; 61 micrel,led-mode = <0>; 70 pinctrl-0 = <&pinctrl_uart2>; 105 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 113 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 114 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 115 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
H A D | mmhub_3_0_0_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_3_0_2_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_4_1_0_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_3_3_0_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_9_1_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0 28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 …RDCLI0__URG_HIGH__SHIFT 0x4 30 …RDCLI0__URG_LOW__SHIFT 0x8 31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 …RDCLI0__MAX_BW__SHIFT 0xd 33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 …DCLI0__MIN_BW__SHIFT 0x16 35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_1_8_0_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_1_0_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0 28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 …RDCLI0__URG_HIGH__SHIFT 0x4 30 …RDCLI0__URG_LOW__SHIFT 0x8 31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 …RDCLI0__MAX_BW__SHIFT 0xd 33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 …DCLI0__MIN_BW__SHIFT 0x16 35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_3_0_1_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_1_7_sh_mask.h | 29 …RDCLI0__VIRT_CHAN__SHIFT 0x0 30 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 …RDCLI0__URG_HIGH__SHIFT 0x4 32 …RDCLI0__URG_LOW__SHIFT 0x8 33 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 …RDCLI0__MAX_BW__SHIFT 0xd 35 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 …DCLI0__MIN_BW__SHIFT 0x16 37 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_9_3_0_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0 28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 …RDCLI0__URG_HIGH__SHIFT 0x4 30 …RDCLI0__URG_LOW__SHIFT 0x8 31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 …RDCLI0__MAX_BW__SHIFT 0xd 33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 …DCLI0__MIN_BW__SHIFT 0x16 35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_2_0_0_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0 28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 …RDCLI0__URG_HIGH__SHIFT 0x4 30 …RDCLI0__URG_LOW__SHIFT 0x8 31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 …RDCLI0__MAX_BW__SHIFT 0xd 33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 …DCLI0__MIN_BW__SHIFT 0x16 35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_9_4_1_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0 28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 …RDCLI0__URG_HIGH__SHIFT 0x4 30 …RDCLI0__URG_LOW__SHIFT 0x8 31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 …RDCLI0__MAX_BW__SHIFT 0xd 33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 …DCLI0__MIN_BW__SHIFT 0x16 35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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H A D | mmhub_2_3_0_sh_mask.h | 27 …RDCLI0__VIRT_CHAN__SHIFT 0x0 28 …RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 29 …RDCLI0__URG_HIGH__SHIFT 0x4 30 …RDCLI0__URG_LOW__SHIFT 0x8 31 …RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 32 …RDCLI0__MAX_BW__SHIFT 0xd 33 …DCLI0__MIN_BW_ENABLE__SHIFT 0x15 34 …DCLI0__MIN_BW__SHIFT 0x16 35 …DCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 36 …DCLI0__MAX_OSD__SHIFT 0x1a [all …]
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/linux/arch/arm64/kernel/ |
H A D | efi-rt-wrapper.S | 32 ldr_l x16, efi_rt_stack_top 33 mov sp, x16 49 mov x16, sp 51 str xzr, [x16, #8] // clear recorded task SP value 56 b.ne 0f 58 0: 77 ldr_l x16, efi_rt_stack_top // clear recorded task SP value 78 str xzr, [x16, #-8]
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H A D | relocate_kernel.S | 52 ldr x16, [x0, #KIMAGE_HEAD] /* x16 = kimage_head */ 57 and x12, x16, PAGE_MASK /* x12 = addr */ 61 tbz x16, IND_SOURCE_BIT, .Ltest_indirection 70 tbz x16, IND_INDIRECTION_BIT, .Ltest_destination 74 tbz x16, IND_DESTINATION_BIT, .Lnext 77 ldr x16, [x14], #8 /* entry = *ptr++ */ 78 tbz x16, IND_DONE_BIT, .Lloop /* while (!(entry & DONE)) */ 93 hvc #0 /* Jumps from el2 */
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/linux/drivers/media/dvb-frontends/ |
H A D | rtl2832_priv.h | 242 {DVBT_DAGC_TRG_VAL, 0x39}, 243 {DVBT_AGC_TARG_VAL_0, 0x0}, 244 {DVBT_AGC_TARG_VAL_8_1, 0x5a}, 245 {DVBT_AAGC_LOOP_GAIN, 0x16}, 246 {DVBT_LOOP_GAIN2_3_0, 0x6}, 247 {DVBT_LOOP_GAIN2_4, 0x1}, 248 {DVBT_LOOP_GAIN3, 0x16}, 249 {DVBT_VTOP1, 0x35}, 250 {DVBT_VTOP2, 0x21}, 251 {DVBT_VTOP3, 0x21}, [all …]
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/linux/drivers/phy/starfive/ |
H A D | phy-jh7110-dphy-tx.c | 26 #define STF_DPHY_AON_POWER_READY_N_ACTIVE 0 27 #define STF_DPHY_AON_POWER_READY_N BIT(0) 43 #define STF_DPHY_RG_CDTX_L4N_HSTX_RES GENMASK(4, 0) 45 #define STF_DPHY_RG_CDTX_PLL_FBK_FRA GENMASK(23, 0) 47 #define STF_DPHY_RG_CDTX_PLL_FBK_INT GENMASK(8, 0) 54 #define STF_DPHY_RG_CLANE_HS_CLK_POST_TIME GENMASK(7, 0) 59 #define STF_DPHY_RG_CLANE_HS_ZERO_TIME GENMASK(7, 0) 64 #define STF_DPHY_RG_EXTD_CYCLE_SEL GENMASK(2, 0) 65 #define STF_DPHY_SCFG_C_HS_PRE_ZERO_TIME GENMASK(31, 0) 100 {160000000, 0x6a, 0xaa, 0x3, 0xa, 0x17, 0x11, 0x5, 0x2b, 0xd, 0x7, 0x3d}, [all …]
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/linux/drivers/mtd/spi-nor/ |
H A D | eon.c | 13 .id = SNOR_ID(0x1c, 0x20, 0x16), 17 .id = SNOR_ID(0x1c, 0x20, 0x17), 21 .id = SNOR_ID(0x1c, 0x30, 0x14), 26 .id = SNOR_ID(0x1c, 0x30, 0x16), 30 .id = SNOR_ID(0x1c, 0x30, 0x17), 35 .id = SNOR_ID(0x1c, 0x31, 0x16), 41 .id = SNOR_ID(0x1c, 0x38, 0x17), 45 .id = SNOR_ID(0x1c, 0x70, 0x15), 50 .id = SNOR_ID(0x1c, 0x70, 0x16), 54 .id = SNOR_ID(0x1c, 0x70, 0x17), [all …]
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