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/freebsd/sys/contrib/device-tree/Bindings/arm/tegra/
H A Dnvidia,tegra20-ahb.txt9 Tegra20, Tegra30, and Tegra114 chips, the value must be <0x6000c004
10 0x10c>. For Tegra124, Tegra132 and Tegra210 chips, the value should
11 be be <0x6000c000 0x150>.
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/freebsd/tools/test/stress2/misc/
H A Dsyzkaller68.sh4 # cpuid = 0
7 # db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe0171ba2510
8 # vpanic() at vpanic+0x150/frame 0xfffffe0171ba2560
9 # panic() at panic+0x43/frame 0xfffffe0171ba25c0
10 # __mtx_assert() at __mtx_assert+0xc4/frame 0xfffffe0171ba25d0
11 # thread_suspend_check() at thread_suspend_check+0x38/frame 0xfffffe0171ba2610
12 # sig_intr() at sig_intr+0x78/frame 0xfffffe0171ba2640
13 # fork1() at fork1+0x238/frame 0xfffffe0171ba26c0
14 # kproc_create() at kproc_create+0x92/frame 0xfffffe0171ba2790
15 # kproc_kthread_add() at kproc_kthread_add+0xdd/frame 0xfffffe0171ba28b0
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Ddm814.h8 #define DM814_CLKCTRL_OFFSET 0x0
12 #define DM814_USB_OTG_HS_CLKCTRL DM814_CLKCTRL_INDEX(0x58)
15 #define DM814_UART1_CLKCTRL DM814_CLKCTRL_INDEX(0x150)
16 #define DM814_UART2_CLKCTRL DM814_CLKCTRL_INDEX(0x154)
17 #define DM814_UART3_CLKCTRL DM814_CLKCTRL_INDEX(0x158)
18 #define DM814_GPIO1_CLKCTRL DM814_CLKCTRL_INDEX(0x15c)
19 #define DM814_GPIO2_CLKCTRL DM814_CLKCTRL_INDEX(0x160)
20 #define DM814_I2C1_CLKCTRL DM814_CLKCTRL_INDEX(0x164)
21 #define DM814_I2C2_CLKCTRL DM814_CLKCTRL_INDEX(0x168)
22 #define DM814_WD_TIMER_CLKCTRL DM814_CLKCTRL_INDEX(0x18c)
[all …]
H A Ddm816.h8 #define DM816_CLKCTRL_OFFSET 0x0
12 #define DM816_USB_OTG_HS_CLKCTRL DM816_CLKCTRL_INDEX(0x58)
15 #define DM816_UART1_CLKCTRL DM816_CLKCTRL_INDEX(0x150)
16 #define DM816_UART2_CLKCTRL DM816_CLKCTRL_INDEX(0x154)
17 #define DM816_UART3_CLKCTRL DM816_CLKCTRL_INDEX(0x158)
18 #define DM816_GPIO1_CLKCTRL DM816_CLKCTRL_INDEX(0x15c)
19 #define DM816_GPIO2_CLKCTRL DM816_CLKCTRL_INDEX(0x160)
20 #define DM816_I2C1_CLKCTRL DM816_CLKCTRL_INDEX(0x164)
21 #define DM816_I2C2_CLKCTRL DM816_CLKCTRL_INDEX(0x168)
22 #define DM816_TIMER1_CLKCTRL DM816_CLKCTRL_INDEX(0x170)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mm-verdin.dtsi23 brightness-levels = <0 45 63 88 119 158 203 255>;
28 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
31 pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>;
38 #clock-cells = <0>;
45 pinctrl-0 = <&pinctrl_gpio_keys>;
64 pinctrl-0 = <&pinctrl_pwm_3_dsi_hpd_gpio>;
105 pinctrl-0 = <&pinctrl_reg_eth>;
136 pinctrl-0 = <&pinctrl_reg_usb1_en>;
148 pinctrl-0 = <&pinctrl_reg_usb2_en>;
161 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
[all …]
H A Dimx8mn-bsh-smm-s2-common.dtsi30 pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
53 pinctrl-0 = <&pinctrl_espi2>;
59 pinctrl-0 = <&pinctrl_fec1>;
68 #size-cells = <0>;
70 ethphy0: ethernet-phy@0 {
72 reg = <0>;
83 pinctrl-0 = <&pinctrl_i2c1>;
88 reg = <0x4b>;
90 pinctrl-0 = <&pinctrl_pmic>;
95 #clock-cells = <0>;
[all...]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mp-venice-gw74xx.dts36 reg = <0x0 0x40000000 0 0x80000000>;
41 pinctrl-0 = <&pinctrl_usbcon1>;
57 key-0 {
67 interrupts = <0>;
102 pinctrl-0 = <&pinctrl_gpio_leds>;
104 led-0 {
122 #clock-cells = <0>;
129 pinctrl-0 = <&pinctrl_pps>;
135 pinctrl-0 = <&pinctrl_reg_usb2>;
147 pinctrl-0 = <&pinctrl_reg_can1>;
[all …]
H A Dimx8mp-tqma8mpql-mba8mpxl.dts26 io-channels = <&adc 0>, <&adc 1>;
44 pinctrl-0 = <&pinctrl_backlight>;
45 pwms = <&pwm2 0 5000000 0>;
46 brightness-levels = <0 4 8 16 32 64 128 255>;
55 #clock-cells = <0>;
64 pinctrl-0 = <&pinctrl_usbcon0>;
77 pinctrl-0 = <&pinctrl_pwmfan>;
81 pwms = <&pwm3 0 40000 PWM_POLARITY_INVERTED>;
82 cooling-levels = <0 32 64 128 196 240>;
92 pinctrl-0 = <&pinctrl_gpiobutton>;
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Daspeed-scu.txt19 reg = <0x1e6e2000 0x1a8>;
47 reg = <0x7c 0x4 0x150 0x8>;
H A Daspeed,ast2x00-scu.yaml45 '^p2a-control@[0-9a-f]+$':
49 '^pinctrl(@[0-9a-f]+)?$':
63 '^interrupt-controller@[0-9a-f]+$':
67 '^silicon-id@[0-9a-f]+$':
105 reg = <0x1e6e2000 0x1a8>;
111 ranges = <0x0 0x1e6e2000 0x1000>;
115 reg = <0x7c 0x4>, <0x150 0x8>;
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300template_xb113.h40 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6];
45 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
50 …{0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written af…
51 0x77, // txrx_mask; //4 bits tx and 4 bits rx
52 { AR9300_OPFLAGS_11A, 0}, // op_cap_flags;
53 0, // rf_silent;
54 0, // blue_tooth_options;
55 0, // device_cap;
58 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
59 0x0d, //feature_enable; //bit0 - enable tx temp comp
[all …]
H A Dar9300template_cus157.h40 {0x00,0x03,0x7f,0x0,0x0,0x0}, //macAddr[6];
45 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
50 …{0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written aft…
51 0x77, // txrxMask; //4 bits tx and 4 bits rx
52 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // opCapFlags;
53 0, // rfSilent;
54 0, // blueToothOptions;
55 0, // deviceCap;
58 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
59 0x0d, //featureEnable; //bit0 - enable tx temp comp
[all …]
H A Dar9300template_hb112.h40 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6];
45 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
50 …{0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written af…
51 0x77, // txrx_mask; //4 bits tx and 4 bits rx
52 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // op_cap_flags;
53 0, // rf_silent;
54 0, // blue_tooth_options;
55 0, // device_cap;
58 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
59 0x0d, //feature_enable; //bit0 - enable tx temp comp
[all …]
H A Dar9300template_ap121.h40 {0x00,0x03,0x7f,0x0,0x0,0x0}, //mac_addr[6];
45 // {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
50 …{0,0x1f}, // reg_dmn[2]; //Does this need to be outside of this structure, if it gets written af…
51 0x11, // txrx_mask; //4 bits tx and 4 bits rx
52 {AR9300_OPFLAGS_11G , 0}, // op_cap_flags;
53 0, // rf_silent;
54 0, // blue_tooth_options;
55 0, // device_cap;
58 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
59 0x0d, //feature_enable; //bit0 - enable tx temp comp
[all …]
H A Dar9300template_osprey_k31.h41 {0,3,0x7f,41,22,0xb4}, //macAddr[6];
46 {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0},
51 …{0,0x1f}, // regDmn[2]; //Does this need to be outside of this structure, if it gets written aft…
52 0x33, // txrxMask; //4 bits tx and 4 bits rx
53 {AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A, 0}, // opCapFlags;
54 0, // rfSilent;
55 0, // blueToothOptions;
56 0, // deviceCap;
59 {0,0}, // params_for_tuning_caps[2]; //placeholder, get more details from Don
60 0x1d, //featureEnable; //bit0 - enable tx temp comp
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/freebsd/contrib/netbsd-tests/lib/libcurses/tests/
H A Dstd_defines8 assign TRUE 0x01
9 assign FALSE 0x00
13 assign COLOR_BLACK 0x00
14 assign COLOR_RED 0x01
15 assign COLOR_GREEN 0x02
16 assign COLOR_YELLOW 0x03
17 assign COLOR_BLUE 0x04
18 assign COLOR_MAGENTA 0x05
19 assign COLOR_CYAN 0x06
20 assign COLOR_WHITE 0x07
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmrvl,intc.txt32 reg = <0xd4282000 0x1000>;
41 reg = <0x150 0x4>, <0x168 0x4>;
62 reg = <0xfed20204 0x04>,
63 <0xfed20214 0x04>;
H A Dmrvl,intc.yaml110 reg = <0xd4282000 0x1000>;
119 reg = <0x150 0x4>, <0x168 0x4>;
128 reg = <0xfed20204 0x04>,
129 <0xfed20214 0x04>;
/freebsd/sys/dev/hwpmc/
H A Dpmu_dmc620_reg.h35 #define DMC620_SNAPSHOT_REQ 0x000 /* WO */
36 #define DMC620_SNAPSHOT_ACK 0x004 /* RO */
37 #define DMC620_OVERFLOW_STATUS_CLKDIV2 0x008 /* RW */
38 #define DMC620_OVERFLOW_STATUS_CLK 0x00C /* RW */
40 #define DMC620_COUNTER_MASK_LO 0x000 /* RW */
41 #define DMC620_COUNTER_MASK_HI 0x004 /* RW */
42 #define DMC620_COUNTER_MATCH_LO 0x008 /* RW */
43 #define DMC620_COUNTER_MATCH_HI 0x00C /* RW */
44 #define DMC620_COUNTER_CONTROL 0x010 /* RW */
45 #define DMC620_COUNTER_CONTROL_ENABLE (1 << 0)
[all …]

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