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Searched +full:0 +full:x14e00000 (Results 1 – 5 of 5) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk.dtsi16 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
62 reg = <0x0c000000 0x600000>;
63 ranges = <0x0 0x0c000000 0x600000>;
68 reg = <0x5f0000 0x8000>;
78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos7.dtsi44 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu_atlas0: cpu@0 {
54 reg = <0x0>;
56 i-cache-size = <0xc000>;
59 d-cache-size = <0x8000>;
68 reg = <0x1>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
82 reg = <0x2>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8188.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x000>;
50 reg = <0x100>;
68 reg = <0x200>;
86 reg = <0x300>;
104 reg = <0x400>;
122 reg = <0x500>;
140 reg = <0x600>;
158 reg = <0x700>;
[all …]
H A Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]