Searched +full:0 +full:x14180000 (Results 1 – 6 of 6) sorted by relevance
47 "p2u-N": where N ranges from 0 to one less than the total number of lanes50 0: C065 - cell 0 specifies the bus and device numbers of the root port:68 - cell 1 denotes the upper 32 address bits and should be 081 - 0x81000000: I/O memory region82 - 0x82000000: non-prefetchable memory region83 - 0xc2000000: prefetchable memory region104 - pinctrl-0: phandle for the 'default' state of pin configuration.147 reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */148 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */[all …]
85 - const: p2u-0123 0: C0132 0 : C0260 bus@0 {263 ranges = <0x0 0x0 0x0 0x8 0x0>;268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */278 linux,pci-domain = <0>;[all …]
39 #size-cells = <0>;88 /* Cluster 0 */89 cpucl0_0: cpu@0 {92 reg = <0x0 0x000>;96 i-cache-size = <0xc000>;99 d-cache-size = <0x8000>;108 reg = <0x0 0x001>;112 i-cache-size = <0xc00[all...]
20 bus@0 {25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;29 reg = <0x0 0x00100000 0x[all...]
19 bus@0 {24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;28 reg = <0x0 0x00100000 0x[all...]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]