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/linux/Documentation/devicetree/bindings/media/
H A Dmediatek-mdp.txt35 reg = <0 0x14001000 0 0x1000>;
45 reg = <0 0x14002000 0 0x1000>;
54 reg = <0 0x14003000 0 0x1000>;
61 reg = <0 0x14004000 0 0x1000>;
68 reg = <0 0x14005000 0 0x1000>;
75 reg = <0 0x14006000 0 0x1000>;
83 reg = <0 0x14007000 0 0x1000>;
91 reg = <0 0x14008000 0 0x1000>;
H A Dmediatek,mdp3-rdma.yaml157 reg = <0x14001000 0x1000>;
158 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmdp_cfg_data.c15 MT8183_MDP_COMP_WPEI = 0,
52 MT8188_MDP_COMP_WPEI = 0,
99 MT8195_MDP_COMP_WPEI = 0,
306 {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, MDP_MM_SUBSYS_0},
307 {0, 0, 0}
311 {0, 0, 0}
315 {0, 0, 0}
319 {0, 0, 0}
322 {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI, MDP_MM_SUBSYS_0},
323 {0, 0, 4}
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g057.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #size-cells = <0>;
27 cpu0: cpu@0 {
29 reg = <0>;
37 reg = <0x100>;
45 reg = <0x200>;
53 reg = <0x300>;
59 L3_CA55: cache-controller-0 {
62 cache-size = <0x100000>;
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1000.h105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]
H A Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]
H A Dmt8183.dtsi293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
[all …]
H A Dmt8186.dtsi329 #size-cells = <0>;
367 cpu0: cpu@0 {
370 reg = <0x000>;
394 reg = <0x100>;
418 reg = <0x200>;
442 reg = <0x300>;
466 reg = <0x400>;
490 reg = <0x500>;
514 reg = <0x600>;
538 reg = <0x700>;
[all …]
H A Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]