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/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-linksys-wrv54g.dts20 memory@0 {
23 reg = <0x00000000 0x2000000>;
67 #size-cells = <0>;
75 switch@0 {
77 reg = <0>;
84 flash@0,0 {
90 reg = <0 0x00000000 0x00800000>;
96 * CHECKME: not using redboot? FIS index 0x3f @7e00000?
100 partition@0 {
102 reg = <0x0 0x140000>;
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Ddra74x.dtsi49 reg = <0x41500000 0x100>;
55 reg = <0x41501000 0x4>,
56 <0x41501010 0x4>,
57 <0x41501014 0x4>;
65 clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
69 ranges = <0x0 0x41501000 0x1000>;
73 mmu0_dsp2: mmu@0 {
75 reg = <0x0 0x100>;
77 #iommu-cells = <0>;
78 ti,syscon-mmuconfig = <&dsp2_system 0x0>;
[all …]
/linux/sound/soc/intel/atom/sst/
H A Dsst_acpi.c38 #define SST_BYT_IRAM_PHY_START 0xff2c0000
39 #define SST_BYT_IRAM_PHY_END 0xff2d4000
40 #define SST_BYT_DRAM_PHY_START 0xff300000
41 #define SST_BYT_DRAM_PHY_END 0xff320000
42 #define SST_BYT_IMR_VIRT_START 0xc0000000 /* virtual addr in LPE */
43 #define SST_BYT_IMR_VIRT_END 0xc01fffff
44 #define SST_BYT_SHIM_PHY_ADDR 0xff340000
45 #define SST_BYT_MBOX_PHY_ADDR 0xff344000
46 #define SST_BYT_DMA0_PHY_ADDR 0xff298000
47 #define SST_BYT_DMA1_PHY_ADDR 0xff29c000
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Drtsm_ve-motherboard-rs2.dtsi15 reg = <0x140000 0x200>;
21 reg = <0x150000 0x200>;
27 reg = <0x200000 0x200>;
/linux/drivers/gpu/drm/xe/regs/
H A Dxe_mchbar_regs.h15 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
19 #define MCHBAR_MIRROR_BASE_SNB 0x140000
21 #define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
22 #define PKG_TDP GENMASK_ULL(14, 0)
30 #define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
31 #define PKG_PWR_UNIT REG_GENMASK(3, 0)
35 #define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
37 #define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
38 #define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
/linux/arch/arm/boot/dts/microchip/
H A Dat91-kizbox3_common.dtsi68 pinctrl-0 = <&pinctrl_pwm0_pwm_h0
76 pwms = <&pwm0 0 10000000 0>;
84 pwms = <&pwm0 1 10000000 0>;
92 pwms = <&pwm0 2 10000000 0>;
99 pwms = <&pwm0 3 10000000 0>;
114 pinctrl-0 = <&pinctrl_ebi_nand_addr>;
116 reg = <0x3 0x0 0x800000>;
118 atmel,rb = <0>;
131 bootstrap@0 {
133 reg = <0x0 0x20000>;
[all …]
H A Dat91sam9x5cm.dtsi11 reg = <0x20000000 0x8000000>;
27 timer@0 {
29 reg = <0>;
40 pinctrl_1wire_cm: 1wire_cm-0 {
52 pinctrl-0 = <&pinctrl_ebi_addr_nand
59 pinctrl-0 = <&pinctrl_nand_oe_we
65 reg = <0x3 0x0 0x800000>;
80 at91bootstrap@0 {
82 reg = <0x0 0x40000>;
87 reg = <0x40000 0xc0000>;
[all …]
H A Dat91-cosino.dtsi24 reg = <0x20000000 0x8000000>;
49 pinctrl-0 = <&pinctrl_ebi_addr_nand
55 pinctrl-0 = <&pinctrl_nand_oe_we
62 reg = <0x3 0x0 0x800000>;
77 at91bootstrap@0 {
79 reg = <0x0 0x40000>;
84 reg = <0x40000 0x80000>;
89 reg = <0xc0000 0x140000>;
94 reg = <0x200000 0x600000>;
99 reg = <0x800000 0x0f800000>;
[all …]
H A Dat91-sam9x60ek.dts40 pinctrl-0 = <&pinctrl_key_gpio_default>;
53 pinctrl-0 = <&pinctrl_gpio_leds>;
110 pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
116 pinctrl-0 = <&pinctrl_can0_rx_tx>;
122 pinctrl-0 = <&pinctrl_can1_rx_tx>;
128 pinctrl-0 = <&pinctrl_classd_default>;
136 pinctrl-0 = <&pinctrl_dbgu>;
142 pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
147 pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
151 reg = <0x3 0x0 0x800000>;
[all …]
H A Dat91-sama5d4_xplained.dts21 reg = <0x20000000 0x20000000>;
51 pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
62 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
66 slot@0 {
67 reg = <0>;
69 cd-gpios = <&pioE 3 0>;
86 cs-gpios = <&pioB 21 0>;
91 timer0: timer@0 {
93 reg = <0>;
104 pinctrl-0 = <
[all …]
H A Dat91-sama5d3_eds.dts26 pinctrl-0 = <&pinctrl_key_gpio>;
31 linux,code = <0x104>;
37 reg = <0x20000000 0x10000000>;
81 pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>;
95 pinctrl-0 = <&pinctrl_ebi_nand_addr>;
103 reg = <0x3 0x0 0x2>;
104 atmel,rb = <0>;
117 at91bootstrap@0 {
119 reg = <0x0 0x40000>;
124 reg = <0x40000 0xc0000>;
[all …]
/linux/sound/soc/sof/intel/
H A Datom.h15 #define IRAM_OFFSET 0x0C0000
17 #define DRAM_OFFSET 0x100000
19 #define SHIM_OFFSET 0x140000
20 #define SHIM_SIZE_BYT 0x100
21 #define SHIM_SIZE_CHT 0x118
22 #define MBOX_OFFSET 0x144000
23 #define MBOX_SIZE 0x1000
24 #define EXCEPT_OFFSET 0x800
25 #define EXCEPT_MAX_HDR_SIZE 0x400
28 #define DMAC0_OFFSET 0x098000
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
H A Dclk-imx8-acm.c135 … IMX_ADMA_ACM_AUD_CLK0_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x000000, 0, 5 },
136 … IMX_ADMA_ACM_AUD_CLK1_SEL, imx8qm_aud_clk_sels, ARRAY_SIZE(imx8qm_aud_clk_sels), 0x010000, 0, 5 },
137 …MX_ADMA_ACM_MCLKOUT0_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x020000, 0, 3 },
138 …MX_ADMA_ACM_MCLKOUT1_SEL, imx8qm_mclk_out_sels, ARRAY_SIZE(imx8qm_mclk_out_sels), 0x030000, 0, 3 },
139 …SRC0_MUX_CLK_SEL, imx8qm_asrc_mux_clk_sels, ARRAY_SIZE(imx8qm_asrc_mux_clk_sels), 0x040000, 0, 2 },
140 …el", IMX_ADMA_ACM_ESAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x060000, 0, 2 },
141 …el", IMX_ADMA_ACM_ESAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x070000, 0, 2 },
142 …sel", IMX_ADMA_ACM_SAI0_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0E0000, 0, 2 },
143 …sel", IMX_ADMA_ACM_SAI1_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x0F0000, 0, 2 },
144 …sel", IMX_ADMA_ACM_SAI2_MCLK_SEL, imx8qm_mclk_sels, ARRAY_SIZE(imx8qm_mclk_sels), 0x100000, 0, 2 },
[all …]
/linux/include/video/
H A Dpmagb-b-fb.h16 #define PMAGB_B_ROM 0x000000 /* REX option ROM */
17 #define PMAGB_B_SFB 0x100000 /* SFB ASIC */
18 #define PMAGB_B_GP0 0x140000 /* general purpose output 0 */
19 #define PMAGB_B_GP1 0x180000 /* general purpose output 1 */
20 #define PMAGB_B_BT459 0x1c0000 /* Bt459 RAMDAC */
21 #define PMAGB_B_FBMEM 0x200000 /* frame buffer */
22 #define PMAGB_B_SIZE 0x400000 /* address space size */
25 #define SFB_REG_VID_HOR 0x64 /* video horizontal setup */
26 #define SFB_REG_VID_VER 0x68 /* video vertical setup */
27 #define SFB_REG_VID_BASE 0x6c /* video base address */
[all …]
/linux/Documentation/devicetree/bindings/cache/
H A Dsocionext,uniphier-system-cache.yaml69 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>;
70 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
72 cache-size = <0x140000>;
82 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>;
83 interrupts = <0 190 4>, <0 191 4>;
85 cache-size = <0x200000>;
94 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>;
95 interrupts = <0 174 4>, <0 175 4>;
97 cache-size = <0x200000>;
/linux/sound/pci/ctxfi/
H A Dct20k1reg.h10 #define DSPXRAM_START 0x000000
11 #define DSPXRAM_END 0x013FFC
12 #define DSPAXRAM_START 0x020000
13 #define DSPAXRAM_END 0x023FFC
14 #define DSPYRAM_START 0x040000
15 #define DSPYRAM_END 0x04FFFC
16 #define DSPAYRAM_START 0x020000
17 #define DSPAYRAM_END 0x063FFC
18 #define DSPMICRO_START 0x080000
19 #define DSPMICRO_END 0x0B3FFC
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-linksys-viper.dts23 reg = <0x00000000 0x8000000>;
36 pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >;
54 pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >;
90 pinctrl-0 = <&pmx_nand>;
98 partition@0 {
100 reg = <0x0 0x80000>;
106 reg = <0x80000 0x20000>;
111 reg = <0xA0000 0x20000>;
116 reg = <0x200000 0x2A0000>;
121 reg = <0x4A0000 0x1760000>;
[all …]
H A Darmada-xp-linksys-mamba.dts6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
34 memory@0 {
36 reg = <0x00000000 0x00000000 0x00000000 0x10000000>; /* 256MB */
40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
42 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
43 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
44 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
64 pinctrl-0 = <&ge0_rgmii_pins>;
69 bm,pool-long = <0>;
[all …]
/linux/arch/loongarch/include/asm/
H A Dcpu.h18 * 31 24 23 16 15 12 11 0
25 #define PRID_COMP_MASK 0xff0000
27 #define PRID_COMP_LOONGSON 0x140000
35 #define PRID_SERIES_MASK 0xf000
37 #define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
38 #define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
39 #define PRID_SERIES_LA364 0xb000 /* Loongson 64bit, 3-issue */
40 #define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
41 #define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
44 * Particular Product ID values for bits 11:0 of the PRID register.
[all …]
/linux/arch/arm/boot/dts/st/
H A Dspear320-hmi.dts18 reg = <0 0x40000000>;
25 pinctrl-0 = <&state_default>;
102 partition@0 {
104 reg = <0x0 0x80000>;
108 reg = <0x80000 0x140000>;
112 reg = <0x1C0000 0x40000>;
116 reg = <0x200000 0x40000>;
120 reg = <0x240000 0xC00000>;
124 reg = <0xE40000 0x0>;
131 #size-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623a-rfb-nand.dts26 cpu@0 {
46 pinctrl-0 = <&key_pins_a>;
63 reg = <0 0x80000000 0 0x20000000>;
103 pinctrl-0 = <&i2s0_pins_a>;
121 port@0 {
150 pinctrl-0 = <&i2c0_pins_a>;
156 pinctrl-0 = <&i2c1_pins_b>;
161 reg = <0x1a>;
167 pinctrl-0 = <&i2c2_pins_b>;
173 pinctrl-0 = <&mmc1_pins_default>;
[all …]
/linux/include/soc/fsl/qe/
H A Dimmap_qe.h26 u8 res0[0x04];
28 u8 res1[0x70];
44 u8 res0[0x4];
47 u8 res1[0x4];
49 u8 res2[0x20];
51 u8 res3[0x1C];
59 u8 res0[0xA];
61 u8 res1[0x2];
66 u8 res2[0x8];
70 u8 res3[0x2];
[all …]
/linux/sound/soc/mediatek/mt8365/
H A Dmt8365-afe-common.h121 MT8365_AFE_APLL1 = 0,
127 MT8365_AFE_1ST_I2S = 0,
133 MT8365_AFE_I2S_SEPARATE_CLOCK = 0,
138 MT8365_AFE_TDM_OUT_I2S = 0,
144 AFE_TDM_CH_START_O28_O29 = 0,
152 MT8365_PCM_FORMAT_I2S = 0,
159 MT8365_FS_8K = 0,
177 FS_8000HZ = 0, /* 0000b */
205 MT8365_AFE_IRQ_DIR_MCU = 0,
212 MT8365_I2S0_MCK = 0,
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov920.dtsi38 #clock-cells = <0>;
44 #size-cells = <0>;
87 cpu0: cpu@0 {
90 reg = <0x0 0x0>;
97 reg = <0x0 0x100>;
104 reg = <0x0 0x200>;
111 reg = <0x0 0x300>;
118 reg = <0x0 0x10000>;
125 reg = <0x0 0x10100>;
132 reg = <0x0 0x10200>;
[all …]

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