Searched +full:0 +full:x13930000 (Results 1 – 8 of 8) sorted by relevance
19 address-cells and size-cells must 1 and 0, respectively.21 decon node or dsi node. The reg value must be 0 and 1 respectively.27 reg = <0x13930000 0x48>;35 #size-cells = <0>;37 port@0 {38 reg = <0>;
20 - pinctrl-0: pin control group to be used for this controller.47 reg = <0x13930000 0x1000>;49 interrupts = <0 188 0>, <0 189 0>, <0 190 0>;62 pinctrl-0 = <&lcd_clk &pwm1_out>;
67 reg = <0x13930000 0x48>;77 #size-cells = <0>;79 port@0 {80 reg = <0>;
47 default: 060 default: 067 default: 0104 reg = <0x13930000 0x1000>;117 pinctrl-0 = <&lcd_clk &pwm1_out>;
199 #size-cells = <0>;212 cpu0: cpu@0 {215 reg = <0>;259 xusbxti: clock-0 {261 clock-frequency = <0>;262 #clock-cells = <0>;268 clock-frequency = <0>;269 #clock-cells = <0>;275 clock-frequency = <0>;276 #clock-cells = <0>;[all …]
68 reg = <0x03810000 0x0c>;79 reg = <0x03830000 0x100>;88 samsung,idma-addr = <0x03000000>;95 reg = <0x10000000 0x100>;100 reg = <0x10500000 0x2000>;105 reg = <0x12570000 0x14>;110 reg = <0x10023c40 0x20>;111 #power-domain-cells = <0>;117 reg = <0x10023c60 0x20>;118 #power-domain-cells = <0>;[all …]
48 #clock-cells = <0>;53 #size-cells = <0>;91 reg = <0x100>;96 i-cache-size = <0x8000>;99 d-cache-size = <0x8000>;109 reg = <0x101>;112 i-cache-size = <0x8000>;115 d-cache-size = <0x8000>;125 reg = <0x102>;128 i-cache-size = <0x8000>;[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]