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/linux/tools/perf/pmu-events/arch/riscv/andes/ax45/
H A Dmicroarch.json3 "EventCode": "0xB1",
8 "EventCode": "0xC1",
13 "EventCode": "0xD1",
18 "EventCode": "0xE1",
23 "EventCode": "0xF1",
28 "EventCode": "0x101",
33 "EventCode": "0x111",
38 "EventCode": "0x121",
43 "EventCode": "0x131",
48 "EventCode": "0x141",
[all …]
/linux/drivers/regulator/
H A Dmt6360-regulator.c19 MT6360_REGULATOR_BUCK1 = 0,
127 REGULATOR_LINEAR_RANGE(300000, 0x00, 0xc7, 5000),
128 REGULATOR_LINEAR_RANGE(1300000, 0xc8, 0xff, 0),
132 REGULATOR_LINEAR_RANGE(500000, 0x00, 0x09, 10000),
133 REGULATOR_LINEAR_RANGE(600000, 0x0a, 0x10, 0),
134 REGULATOR_LINEAR_RANGE(610000, 0x11, 0x19, 10000),
135 REGULATOR_LINEAR_RANGE(700000, 0x1a, 0x20, 0),
136 REGULATOR_LINEAR_RANGE(710000, 0x21, 0x29, 10000),
137 REGULATOR_LINEAR_RANGE(800000, 0x2a, 0x30, 0),
138 REGULATOR_LINEAR_RANGE(810000, 0x31, 0x39, 10000),
[all …]
/linux/Documentation/devicetree/bindings/leds/
H A Dqcom,pm8058-led.yaml48 #size-cells = <0>;
52 reg = <0x131>;
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphyreg_n.h6 #define NPHY_TBL_ID_GAIN1 0
27 #define NPHY_TO_BPHY_OFF 0xc00
29 #define NPHY_BandControl_currentBand 0x0001
30 #define RFCC_CHIP0_PU 0x0400
31 #define RFCC_POR_FORCE 0x0040
32 #define RFCC_OE_POR_FORCE 0x0080
33 #define NPHY_RfctrlIntc_override_OFF 0
38 #define RIFS_ENABLE 0x80
39 #define BPHY_BAND_SEL_UP20 0x10
40 #define NPHY_MLenable 0x02
[all …]
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dtrap.h9 MLXSW_TRAP_ID_FDB_MC = 0x01,
10 MLXSW_TRAP_ID_ETHEMAD = 0x05,
12 MLXSW_TRAP_ID_STP = 0x10,
13 MLXSW_TRAP_ID_LACP = 0x11,
14 MLXSW_TRAP_ID_EAPOL = 0x12,
15 MLXSW_TRAP_ID_LLDP = 0x13,
16 MLXSW_TRAP_ID_MMRP = 0x14,
17 MLXSW_TRAP_ID_MVRP = 0x15,
18 MLXSW_TRAP_ID_RPVST = 0x16,
19 MLXSW_TRAP_ID_DHCP = 0x19,
[all …]
/linux/drivers/char/hw_random/
H A Dn2rng.h11 #define RNG_v1_CTL_WAIT 0x0000000001fffe00ULL /* Minimum wait time */
13 #define RNG_v1_CTL_BYPASS 0x0000000000000100ULL /* VCO voltage source */
14 #define RNG_v1_CTL_VCO 0x00000000000000c0ULL /* VCO rate control */
16 #define RNG_v1_CTL_ASEL 0x0000000000000030ULL /* Analog MUX select */
21 #define RNG_CTL_LFSR 0x0000000000000008ULL /* Use LFSR or plain shift */
22 #define RNG_CTL_ES3 0x0000000000000004ULL /* Enable entropy source 3 */
23 #define RNG_CTL_ES2 0x0000000000000002ULL /* Enable entropy source 2 */
24 #define RNG_CTL_ES1 0x0000000000000001ULL /* Enable entropy source 1 */
27 #define RNG_v2_CTL_WAIT 0x0000000007fff800ULL /* Minimum wait time */
29 #define RNG_v2_CTL_BYPASS 0x0000000000000400ULL /* VCO voltage source */
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dpm8058.dtsi9 #size-cells = <0>;
13 reg = <0x1c>;
22 reg = <0x48>;
28 reg = <0x4a>;
34 reg = <0x50>;
37 gpio-ranges = <&pm8058_mpps 0 0 12>;
44 reg = <0x131>;
50 reg = <0x132>;
56 reg = <0x133>;
62 reg = <0x148>;
[all …]
/linux/arch/sparc/crypto/
H A Dopcodes.h9 #define FPD_ENCODE(x) (((x) >> 5) | ((x) & ~(0x20)))
12 #define RS2(x) (FPD_ENCODE(x) << 0)
15 #define IMM5_0(x) ((x) << 0)
19 .word (F3F(2,0x36,0x147)|RS1(a)|RS2(b)|RD(c));
22 .word 0x81b02800;
24 .word 0x81b02820;
26 .word 0x81b02840;
28 .word 0x81b02860;
31 .word (F3F(2, 0x19, 0)|RS1(a)|RS2(b)|RS3(c)|RD(d));
33 .word (F3F(2, 0x19, 1)|RS1(a)|RS2(b)|RS3(c)|RD(d));
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_devtbl.h2 #define QLA_MODEL_NAMES 0x5C
8 "QLA2340", "133MHz PCI-X to 2Gb FC, Single Channel", /* 0x100 */
9 "QLA2342", "133MHz PCI-X to 2Gb FC, Dual Channel", /* 0x101 */
10 "QLA2344", "133MHz PCI-X to 2Gb FC, Quad Channel", /* 0x102 */
11 "QCP2342", "cPCI to 2Gb FC, Dual Channel", /* 0x103 */
12 "QSB2340", "SBUS to 2Gb FC, Single Channel", /* 0x104 */
13 "QSB2342", "SBUS to 2Gb FC, Dual Channel", /* 0x105 */
14 "QLA2310", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x106 */
15 "QLA2332", "Sun 66MHz PCI-X to 2Gb FC, Single Channel", /* 0x107 */
16 "QCP2332", "Sun cPCI to 2Gb FC, Dual Channel", /* 0x108 */
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/linux/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/linux/drivers/hid/
H A Dwacom_wac.h38 #define STYLUS_DEVICE_ID 0x02
39 #define TOUCH_DEVICE_ID 0x03
40 #define CURSOR_DEVICE_ID 0x06
41 #define ERASER_DEVICE_ID 0x0A
42 #define PAD_DEVICE_ID 0x0F
73 #define WAC_CMD_WL_LED_CONTROL 0x03
74 #define WAC_CMD_LED_CONTROL 0x20
75 #define WAC_CMD_ICON_START 0x21
76 #define WAC_CMD_ICON_XFER 0x23
77 #define WAC_CMD_ICON_BT_XFER 0x26
[all …]
/linux/include/linux/mfd/da9062/
H A Dregisters.h9 #define DA9062_PMIC_DEVICE_ID 0x62
10 #define DA9062_PMIC_VARIANT_MRC_AA 0x01
11 #define DA9062_PMIC_VARIANT_VRC_DA9061 0x01
12 #define DA9062_PMIC_VARIANT_VRC_DA9062 0x02
20 #define DA9062AA_PAGE_CON 0x000
21 #define DA9062AA_STATUS_A 0x001
22 #define DA9062AA_STATUS_B 0x002
23 #define DA9062AA_STATUS_D 0x004
24 #define DA9062AA_FAULT_LOG 0x005
25 #define DA9062AA_EVENT_A 0x006
[all …]
/linux/drivers/perf/arm_cspmu/
H A Dnvidia_cspmu.c15 #define NV_PCIE_FILTER_ID_MASK GENMASK_ULL(NV_PCIE_PORT_COUNT - 1, 0)
18 #define NV_NVL_C2C_FILTER_ID_MASK GENMASK_ULL(NV_NVL_C2C_PORT_COUNT - 1, 0)
21 #define NV_CNVL_FILTER_ID_MASK GENMASK_ULL(NV_CNVL_PORT_COUNT - 1, 0)
23 #define NV_GENERIC_FILTER_ID_MASK GENMASK_ULL(31, 0)
25 #define NV_PRODID_MASK GENMASK(31, 0)
27 #define NV_FORMAT_NAME_GENERIC 0
49 ARM_CSPMU_EVENT_ATTR(bus_cycles, 0x1d),
51 ARM_CSPMU_EVENT_ATTR(scf_cache_allocate, 0xF0),
52 ARM_CSPMU_EVENT_ATTR(scf_cache_refill, 0xF1),
53 ARM_CSPMU_EVENT_ATTR(scf_cache, 0xF2),
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2057.h9 #define R2057_DACBUF_VINCM_CORE0 0x000
10 #define R2057_IDCODE 0x001
11 #define R2057_RCCAL_MASTER 0x002
12 #define R2057_RCCAL_CAP_SIZE 0x003
13 #define R2057_RCAL_CONFIG 0x004
14 #define R2057_GPAIO_CONFIG 0x005
15 #define R2057_GPAIO_SEL1 0x006
16 #define R2057_GPAIO_SEL0 0x007
17 #define R2057_CLPO_CONFIG 0x008
18 #define R2057_BANDGAP_CONFIG 0x009
[all …]
/linux/arch/sparc/kernel/
H A Dttable_64.S17 tl0_resv000: BOOT_KERNEL BTRAP(0x1) BTRAP(0x2) BTRAP(0x3)
18 tl0_resv004: BTRAP(0x4) BTRAP(0x5) BTRAP(0x6) BTRAP(0x7)
24 tl0_resv00b: BTRAP(0xb) BTRAP(0xc) BTRAP(0xd) BTRAP(0xe) BTRAP(0xf)
28 tl0_resv012: BTRAP(0x12) BTRAP(0x13) BTRAP(0x14) BTRAP(0x15) BTRAP(0x16) BTRAP(0x17)
29 tl0_resv018: BTRAP(0x18) BTRAP(0x19)
31 tl0_resv01b: BTRAP(0x1b)
32 tl0_resv01c: BTRAP(0x1c) BTRAP(0x1d) BTRAP(0x1e) BTRAP(0x1f)
39 tl0_resv029: BTRAP(0x29) BTRAP(0x2a) BTRAP(0x2b) BTRAP(0x2c) BTRAP(0x2d) BTRAP(0x2e)
40 tl0_resv02f: BTRAP(0x2f)
45 tl0_resv033: BTRAP(0x33)
[all …]
/linux/arch/x86/math-emu/
H A Dget_address.c30 #define FPU_WRITE_BIT 0x10
71 /* Decode the SIB byte. This function assumes mod != 0 */
86 if ((mod == 0) && (base == 5)) in sib()
87 offset = 0; /* No base register */ in sib()
109 } else if (mod == 2 || base == 5) { /* The second condition also has mod==0 */ in sib()
128 EXCEPTION(EX_INTERNAL | 0x130); in vm86_segment()
146 /* segment is unsigned, so this also detects if segment was 0: */ in pm_address()
148 EXCEPTION(EX_INTERNAL | 0x132); in pm_address()
169 limit = 0xffffffff; in pm_address()
173 seg_top = 0xffffffff; in pm_address()
[all …]
H A Derrors.c37 #if 0
49 if ((byte1 & 0xf8) == 0xd8)
58 printk("%02x (%02x+%d)\n", FPU_modrm, FPU_modrm & 0xf8,
71 #endif /* 0 */
96 for (i = 0; i < MAX_PRINTED_BYTES; i++) { in FPU_printall()
98 if ((byte1 & 0xf8) == 0xd8) { in FPU_printall()
112 FPU_modrm & 0xf8, FPU_modrm & 7); in FPU_printall()
134 printk("SW: condition bit 0\n"); in FPU_printall()
153 … b=%d st=%d es=%d sf=%d cc=%d%d%d%d ef=%d%d%d%d%d%d\n", partial_status & 0x8000 ? 1 : 0, /* busy */ in FPU_printall()
154 (partial_status & 0x3800) >> 11, /* stack top pointer */ in FPU_printall()
[all …]
/linux/sound/drivers/opl4/
H A Dyrw801.c40 snd_opl4_read_memory(opl4, buf, 0x001200, 15); in snd_yrw801_detect()
43 snd_opl4_read_memory(opl4, buf, 0x1ffffe, 2); in snd_yrw801_detect()
44 if (buf[0] != 0x01) in snd_yrw801_detect()
46 dev_dbg(opl4->card->dev, "YRW801 ROM version %02x.%02x\n", buf[0], buf[1]); in snd_yrw801_detect()
47 return 0; in snd_yrw801_detect()
58 {0x14, 0x27, {0x12c,7474,100, 0,0,0x00,0xc8,0x20,0xf2,0x13,0x08,0x0}},
59 {0x28, 0x2d, {0x12d,6816,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
60 {0x2e, 0x33, {0x12e,5899,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
61 {0x34, 0x39, {0x12f,5290,100, 0,0,0x00,0xc8,0x20,0xf2,0x14,0x08,0x0}},
62 {0x3a, 0x3f, {0x130,4260,100, 0,0,0x0a,0xc8,0x20,0xf2,0x14,0x08,0x0}},
[all …]
H A Dopl4_synth.c41 #define MIDI_CTL_RELEASE_TIME 0x48
42 #define MIDI_CTL_ATTACK_TIME 0x49
43 #define MIDI_CTL_DECAY_TIME 0x4b
44 #define MIDI_CTL_VIBRATO_RATE 0x4c
45 #define MIDI_CTL_VIBRATO_DEPTH 0x4d
46 #define MIDI_CTL_VIBRATO_DELAY 0x4e
52 static const s16 snd_opl4_pitch_map[0x600] = {
53 0x000,0x000,0x001,0x001,0x002,0x002,0x003,0x003,
54 0x004,0x004,0x005,0x005,0x006,0x006,0x006,0x007,
55 0x007,0x008,0x008,0x009,0x009,0x00a,0x00a,0x00b,
[all …]
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu7_ppsmc.h30 #define PPSMC_MSG_SetGBDroopSettings ((uint16_t) 0x305)
32 #define PPSMC_SWSTATE_FLAG_DC 0x01
33 #define PPSMC_SWSTATE_FLAG_UVD 0x02
34 #define PPSMC_SWSTATE_FLAG_VCE 0x04
36 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
37 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
38 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
40 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
41 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
42 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
H A Dtonga_ppsmc.h29 #define PPSMC_SWSTATE_FLAG_DC 0x01
30 #define PPSMC_SWSTATE_FLAG_UVD 0x02
31 #define PPSMC_SWSTATE_FLAG_VCE 0x04
32 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
H A Dfiji_ppsmc.h30 #define PPSMC_SWSTATE_FLAG_DC 0x01
31 #define PPSMC_SWSTATE_FLAG_UVD 0x02
32 #define PPSMC_SWSTATE_FLAG_VCE 0x04
34 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
35 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
36 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
38 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
39 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
40 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
42 #define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
[all …]
/linux/drivers/net/wan/
H A Dhd64572.h4 * CPU modes 0 & 2.
15 * PC300 initial CVS version (3.4.0-pre1)
25 #define ILAR 0x00
28 #define PABR0L 0x20 /* Physical Addr Boundary Register 0 L */
29 #define PABR0H 0x21 /* Physical Addr Boundary Register 0 H */
30 #define PABR1L 0x22 /* Physical Addr Boundary Register 1 L */
31 #define PABR1H 0x23 /* Physical Addr Boundary Register 1 H */
32 #define WCRL 0x24 /* Wait Control Register L */
33 #define WCRM 0x25 /* Wait Control Register M */
34 #define WCRH 0x26 /* Wait Control Register H */
[all …]
/linux/include/linux/mfd/da9063/
H A Dregisters.h18 /* Page 0 : I2C access 0x000 - 0x0FF SPI access 0x000 - 0x07F */
19 /* Page 1 : SPI access 0x080 - 0x0FF */
20 /* Page 2 : I2C access 0x100 - 0x1FF SPI access 0x100 - 0x17F */
21 /* Page 3 : SPI access 0x180 - 0x1FF */
22 #define DA9063_REG_PAGE_CON 0x00
25 #define DA9063_REG_STATUS_A 0x01
26 #define DA9063_REG_STATUS_B 0x02
27 #define DA9063_REG_STATUS_C 0x03
28 #define DA9063_REG_STATUS_D 0x04
29 #define DA9063_REG_FAULT_LOG 0x05
[all …]

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