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/freebsd/sys/dev/clk/allwinner/
H A Dccu_h6_r.c55 CCU_RESET(RST_R_APB1_TIMER, 0x11c, 16)
56 CCU_RESET(RST_R_APB1_TWD, 0x12c, 16)
57 CCU_RESET(RST_R_APB1_PWM, 0x13c, 16)
58 CCU_RESET(RST_R_APB2_UART, 0x18c, 16)
59 CCU_RESET(RST_R_APB2_I2C, 0x19c, 16)
60 CCU_RESET(RST_R_APB1_IR, 0x1cc, 16)
61 CCU_RESET(RST_R_APB1_W1, 0x1ec, 16)
65 CCU_GATE(CLK_R_APB1_TIMER, "r_apb1-timer", "r_apb1", 0x11c, 0)
66 CCU_GATE(CLK_R_APB1_TWD, "r_apb1-twd", "r_apb1", 0x12c, 0)
67 CCU_GATE(CLK_R_APB1_PWM, "r_apb1-pwm", "r_apb1", 0x13c, 0)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/vf/
H A Dvf610-pinfunc.h14 #define ALT0 0x0
15 #define ALT1 0x1
16 #define ALT2 0x2
17 #define ALT3 0x3
18 #define ALT4 0x4
19 #define ALT5 0x5
20 #define ALT6 0x6
21 #define ALT7 0x7
24 #define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
25 #define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx6dl-pinfunc.h13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/freebsd/sys/arm/ti/
H A Dti_spireg.h32 #define MCSPI_REVISION 0x0
34 #define MCSPI_REVISION_SCHEME_MSK 0x3
36 #define MCSPI_REVISION_FUNC_MSK 0xfff
38 #define MCSPI_REVISION_RTL_MSK 0x1f
40 #define MCSPI_REVISION_MAJOR_MSK 0x7
42 #define MCSPI_REVISION_CUSTOM_MSK 0x3
43 #define MCSPI_REVISION_MINOR_SHIFT 0
44 #define MCSPI_REVISION_MINOR_MSK 0x3f
45 #define MCSPI_SYSCONFIG 0x110
47 #define MCSPI_SYSSTATUS 0x114
[all …]
/freebsd/sys/dev/xilinx/
H A Dxlnx_pcib.h36 #define XLNX_PCIE_VSEC 0x12c
37 #define XLNX_PCIE_BIR 0x130 /* Bridge Info Register */
38 #define XLNX_PCIE_BSCR 0x134 /* Bridge Status and Control */
39 #define XLNX_PCIE_IDR 0x138 /* Interrupt Decode Register */
40 #define XLNX_PCIE_IMR 0x13C /* Interrupt Mask Register */
41 #define IMR_LINK_DOWN (1 << 0)
44 #define IMR_CFG_COMPL_STATUS_M (0x7 << IMR_CFG_COMPL_STATUS_S)
59 #define XLNX_PCIE_BLR 0x140 /* Bus Location Register */
60 #define XLNX_PCIE_PHYSCR 0x144 /* PHY Status/Control Register */
62 #define XLNX_PCIE_RPSCR 0x148 /* Root Port Status/Control Register */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap4-kc1.dts15 reg = <0x80000000 0x20000000>; /* 512 MB */
23 pwms = <&twl_pwm 0 7812500>;
40 OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */
41 OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */
47 OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
48 OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
54 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
55 OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
61 OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
62 OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
[all …]
H A Domap4-duovero-parlor.dts31 #size-cells = <0>;
59 pinctrl-0 = <
67 OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3) /* abe_dmic_din3.gpio_122 */
73 OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* abe_dmic_din2.gpio_121 */
79 OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
80 OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
86 OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
87 OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
93 OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3) /* gpmc_a20.gpio_44: IRQ */
94 OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a21.gpio_45: nReset */
[all …]
H A Dam3517-som.dtsi10 cpu@0 {
21 pinctrl-0 = <&wl12xx_buffer_pins>;
33 pinctrl-0 = <&wl12xx_wkup_pins>;
43 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
45 nand@0,0 {
48 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
51 gpmc,sync-clk-ps = <0>;
52 gpmc,cs-on-ns = <0>;
64 gpmc,wr-data-mux-bus-ns = <0>;
73 pinctrl-0 = <&i2c1_pins>;
[all …]
H A Domap4-var-som-om44.dtsi15 reg = <0x80000000 0x40000000>; /* 1 GB */
38 pinctrl-0 = <
45 #phy-cells = <0>;
64 pinctrl-0 = <
70 OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3) /* fref_clk2_out.gpio_182 */
71 OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
77 OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3) /* gpmc_ncs4.gpio_101 (irq) */
78 OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3) /* gpmc_ncs5.gpio_102 (rst) */
84 OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
85 OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhikey-pinctrl.dtsi12 pinctrl-0 = <
22 0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
28 0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
29 0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
30 0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
31 0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
32 0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
33 0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
34 0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
35 0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
[all …]
/freebsd/sys/dev/bhnd/cores/pcie2/
H A Dbhnd_pcie2_reg.h31 #define BHND_PCIE2_DMA64_TRANSLATION 0x8000000000000000 /**< PCIe-Gen2 DMA64 address translation */
32 #define BHND_PCIE2_DMA64_MASK 0xc000000000000000 /**< PCIe-Gen2 DMA64 translation mask */
38 #define BHND_PCIE2_CLK_CONTROL 0x000
40 #define BHND_PCIE2_RC_PM_CONTROL 0x004
41 #define BHND_PCIE2_RC_PM_STATUS 0x008
42 #define BHND_PCIE2_EP_PM_CONTROL 0x00C
43 #define BHND_PCIE2_EP_PM_STATUS 0x010
44 #define BHND_PCIE2_EP_LTR_CONTROL 0x014
45 #define BHND_PCIE2_EP_LTR_STATUS 0x018
46 #define BHND_PCIE2_EP_OBFF_STATUS 0x01C
[all …]
/freebsd/sys/dev/bhnd/cores/pci/
H A Dbhnd_pcireg.h32 #define BHND_PCI_DMA32_TRANSLATION 0x40000000 /**< PCI DMA32 address translation (sbtopci2) */
35 #define BHND_PCIE_DMA32_TRANSLATION 0x80000000 /**< PCIe-Gen1 DMA32 address translation (sb2pcitr…
45 #define BHND_PCI_CTL 0x000 /**< PCI core control*/
46 #define BHND_PCI_ARB_CTL 0x010 /**< PCI arbiter control */
47 #define BHND_PCI_CLKRUN_CTL 0x014 /**< PCI clckrun control (>= rev11) */
48 #define BHND_PCI_INTR_STATUS 0x020 /**< Interrupt status */
49 #define BHND_PCI_INTR_MASK 0x024 /**< Interrupt mask */
50 #define BHND_PCI_SBTOPCI_MBOX 0x028 /**< Sonics to PCI mailbox */
51 #define BHND_PCI_BCAST_ADDR 0x050 /**< Sonics broadcast address (pci) */
52 #define BHND_PCI_BCAST_DATA 0x054 /**< Sonics broadcast data (pci) */
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/
H A DAArch64.def7 // Null relocation: also 0x100 for ELF64
8 ELF_RELOC(R_AARCH64_NONE, 0)
10 ELF_RELOC(R_AARCH64_ABS64, 0x101)
11 ELF_RELOC(R_AARCH64_ABS32, 0x102)
12 ELF_RELOC(R_AARCH64_ABS16, 0x103)
13 ELF_RELOC(R_AARCH64_PREL64, 0x104)
14 ELF_RELOC(R_AARCH64_PREL32, 0x105)
15 ELF_RELOC(R_AARCH64_PREL16, 0x106)
17 ELF_RELOC(R_AARCH64_MOVW_UABS_G0, 0x107)
18 ELF_RELOC(R_AARCH64_MOVW_UABS_G0_NC, 0x108)
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j721e-evm-gesi-exp-board.dtso31 pinctrl-0 = <&rgmii1_default_pins
72 pinctrl-0 = <&mdio0_default_pins>;
75 #size-cells = <0>;
77 cpsw9g_phy0: ethernet-phy@0 {
78 reg = <0>;
124 J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
125 J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
131 J721E_IOPAD(0x4, PIN_INPUT, 4) /* (AC23) PRG1_PRU0_GPO0.RGMII1_RD0 */
132 J721E_IOPAD(0x8, PIN_INPUT, 4) /* (AG22) PRG1_PRU0_GPO1.RGMII1_RD1 */
133 J721E_IOPAD(0xc, PIN_INPUT, 4) /* (AF22) PRG1_PRU0_GPO2.RGMII1_RD2 */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/
H A Diwl-context-info-gen3.h10 #define CSR_CTXT_INFO_BOOT_CTRL 0x0
11 #define CSR_CTXT_INFO_ADDR 0x118
12 #define CSR_IML_DATA_ADDR 0x120
13 #define CSR_IML_SIZE_ADDR 0x128
14 #define CSR_IML_RESP_ADDR 0x12c
31 IWL_PRPH_MTR_FORMAT_16B = 0x0,
32 IWL_PRPH_MTR_FORMAT_32B = 0x40000,
33 IWL_PRPH_MTR_FORMAT_64B = 0x80000,
34 IWL_PRPH_MTR_FORMAT_256B = 0xC000
[all...]

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