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/linux/Documentation/devicetree/bindings/display/panel/
H A Draydium,rm68200.yaml13 The Raydium Semiconductor Corporation RM68200 is a 5.5" 720x1280 TFT LCD
47 #size-cells = <0>;
48 panel@0 {
50 reg = <0>;
51 reset-gpios = <&gpiof 15 0>;
H A Dxinpeng,xpp055c272.yaml7 title: Xinpeng XPP055C272 5.5in 720x1280 DSI panel
44 #size-cells = <0>;
46 panel@0 {
48 reg = <0>;
H A Drocktech,jh057n00900.yaml27 # Powkiddy RGB10MAX3 5.0" 720x1280 TFT LCD panel
67 #size-cells = <0>;
68 panel@0 {
70 reg = <0>;
H A Dpanel-edp-legacy.yaml61 # LG 12.0" (1920x1280 pixels) TFT LCD panel
104 hsync-active = <0>;
109 vsync-active = <0>;
/linux/include/linux/soc/samsung/
H A Dexynos-regs-pmu.h17 #define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200
21 #define S5P_CENTRAL_SEQ_OPTION 0x0208
42 #define EXYNOS_SWRESET 0x0400
44 #define S5P_WAKEUP_STAT 0x0600
46 #define EXYNOS_EINT_WAKEUP_MASK_DISABLED 0xffffffff
47 #define EXYNOS_EINT_WAKEUP_MASK 0x0604
48 #define S5P_WAKEUP_MASK 0x0608
49 #define S5P_WAKEUP_MASK2 0x0614
52 #define EXYNOS4_MIPI_PHY_CONTROL(n) (0x0710 + (n) * 4)
54 #define EXYNOS4_PHY_ENABLE (1 << 0)
[all …]
/linux/include/uapi/linux/
H A Dcycx_cfm.h28 #define CFM_IMAGE_SIZE 0x20000 /* max size of CYCX code image file */
31 #define CFM_LOAD_BUFSZ 0x400 /* buffer size for reset code (buffer_load) */
34 #define GEN_POWER_ON 0x1280
36 #define GEN_SET_SEG 0x1401 /* boot segment setting. */
37 #define GEN_BOOT_DAT 0x1402 /* boot data. */
38 #define GEN_START 0x1403 /* board start. */
39 #define GEN_DEFPAR 0x1404 /* buffer length for boot. */
/linux/sound/soc/mediatek/mt2701/
H A Dmt2701-reg.h12 #define AUDIO_TOP_CON0 0x0000
13 #define AUDIO_TOP_CON4 0x0010
14 #define AUDIO_TOP_CON5 0x0014
15 #define AFE_DAIBT_CON0 0x001c
16 #define AFE_MRGIF_CON 0x003c
17 #define ASMI_TIMING_CON1 0x0100
18 #define ASMO_TIMING_CON1 0x0104
19 #define PWR1_ASM_CON1 0x0108
20 #define ASYS_TOP_CON 0x0600
21 #define ASYS_I2SIN1_CON 0x0604
[all …]
/linux/drivers/irqchip/
H A Dirq-clps711x.c19 #define CLPS711X_INTSR1 (0x0240)
20 #define CLPS711X_INTMR1 (0x0280)
21 #define CLPS711X_BLEOI (0x0600)
22 #define CLPS711X_MCEOI (0x0640)
23 #define CLPS711X_TEOI (0x0680)
24 #define CLPS711X_TC1EOI (0x06c0)
25 #define CLPS711X_TC2EOI (0x0700)
26 #define CLPS711X_RTCEOI (0x0740)
27 #define CLPS711X_UMSEOI (0x0780)
28 #define CLPS711X_COEOI (0x07c0)
[all …]
/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic_reg.h13 #define NIC_PF_CFG (0x0000)
14 #define NIC_PF_STATUS (0x0010)
15 #define NIC_PF_INTR_TIMER_CFG (0x0030)
16 #define NIC_PF_BIST_STATUS (0x0040)
17 #define NIC_PF_SOFT_RESET (0x0050)
18 #define NIC_PF_TCP_TIMER (0x0060)
19 #define NIC_PF_BP_CFG (0x0080)
20 #define NIC_PF_RRM_CFG (0x0088)
21 #define NIC_PF_CQM_CFG (0x00A0)
22 #define NIC_PF_CNM_CF (0x00A8)
[all …]
/linux/drivers/video/backlight/
H A Dotm3225a.c22 #define OTM3225A_INDEX_REG 0x70
23 #define OTM3225A_DATA_REG 0x72
26 #define DRIVER_OUTPUT_CTRL_1 0x01
27 #define DRIVER_WAVEFORM_CTRL 0x02
28 #define ENTRY_MODE 0x03
29 #define SCALING_CTRL 0x04
30 #define DISPLAY_CTRL_1 0x07
31 #define DISPLAY_CTRL_2 0x08
32 #define DISPLAY_CTRL_3 0x09
33 #define FRAME_CYCLE_CTRL 0x0A
[all …]
/linux/arch/s390/include/asm/
H A Dlowcore.h23 #define LOWCORE_ALT_ADDRESS _AC(0x70000, UL)
32 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
33 __u32 ipl_parmblock_ptr; /* 0x0014 */
34 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
35 __u32 ext_params; /* 0x0080 */
38 __u16 ext_cpu_addr; /* 0x0084 */
39 __u16 ext_int_code; /* 0x0086 */
43 __u32 svc_int_code; /* 0x0088 */
46 __u16 pgm_ilc; /* 0x008c */
47 __u16 pgm_code; /* 0x008e */
[all …]
/linux/drivers/media/pci/cx25821/
H A Dcx25821-medusa-reg.h13 #define HOST_REGISTER1 0x0000
14 #define HOST_REGISTER2 0x0001
17 #define CHIP_CTRL 0x0100
18 #define AFE_AB_CTRL 0x0104
19 #define AFE_CD_CTRL 0x0108
20 #define AFE_EF_CTRL 0x010C
21 #define AFE_GH_CTRL 0x0110
22 #define DENC_AB_CTRL 0x0114
23 #define BYP_AB_CTRL 0x0118
24 #define MON_A_CTRL 0x011C
[all …]
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_regs.h24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
[all …]
/linux/drivers/clk/stm32/
H A Dstm32mp21_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
H A Dstm32mp25_rcc.h10 #define RCC_SECCFGR0 0x0
11 #define RCC_SECCFGR1 0x4
12 #define RCC_SECCFGR2 0x8
13 #define RCC_SECCFGR3 0xC
14 #define RCC_PRIVCFGR0 0x10
15 #define RCC_PRIVCFGR1 0x14
16 #define RCC_PRIVCFGR2 0x18
17 #define RCC_PRIVCFGR3 0x1C
18 #define RCC_RCFGLOCKR0 0x20
19 #define RCC_RCFGLOCKR1 0x24
[all …]
/linux/include/linux/
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/linux/drivers/net/fddi/
H A Ddefxx.h70 #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */
75 #define PI_PHY_K_S 0 /* Index to S phy */
76 #define PI_PHY_K_A 0 /* Index to A phy */
95 #define PI_FMC_DESCR_V_LEN 0
97 #define PI_FMC_DESCR_M_SOP 0x80000000
98 #define PI_FMC_DESCR_M_EOP 0x40000000
99 #define PI_FMC_DESCR_M_FSC 0x38000000
100 #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000
101 #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000
102 #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h16 #define ID_REV (0x00)
17 #define ID_REV_ID_MASK_ (0xFFFF0000)
18 #define ID_REV_ID_LAN7430_ (0x74300000)
19 #define ID_REV_ID_LAN7431_ (0x74310000)
20 #define ID_REV_ID_LAN743X_ (0x74300000)
21 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
22 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
23 #define ID_REV_ID_A0X1_ (0xA0010000)
25 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
26 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
[all …]
/linux/drivers/atm/
H A Dhe.c50 group 0 is used for all traffic
51 interrupt queue 0 is used for all interrupts
93 #define HPRINTK(fmt,args...) do { } while (0)
126 CLK_HIGH, /* 0 */
128 CLK_HIGH, /* 0 */
130 CLK_HIGH, /* 0 */
132 CLK_HIGH, /* 0 */
134 CLK_HIGH, /* 0 */
136 CLK_HIGH, /* 0 */
176 #define he_writel(dev, val, reg) do { writel(val, (dev)->membase + (reg)); wmb(); } while (0)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8974.dtsi23 #clock-cells = <0>;
29 #clock-cells = <0>;
36 #size-cells = <0>;
39 cpu0: cpu@0 {
43 reg = <0>;
109 memory@0 {
111 reg = <0x0 0x0>;
136 mboxes = <&apcs 0>;
159 reg = <0x08000000 0x5100000>;
164 reg = <0x0d100000 0x100000>;
[all …]

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