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/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_hw.c15 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
19 #define CRB_BLK(off) ((off >> 20) & 0x3f)
20 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
21 #define CRB_WINDOW_2M (0x130060)
22 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
23 #define CRB_INDIRECT_2M (0x1e0000UL)
52 {{{0, 0, 0, 0} } }, /* 0: PCI */
53 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
54 {1, 0x0110000, 0x0120000, 0x130000},
55 {1, 0x0120000, 0x0122000, 0x124000},
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7925/
H A Dpci.c15 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7925),
17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0717),
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7927),
21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x6639),
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0738),
25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7928),
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7935),
73 dev->backup_l1 = 0; in mt7925_reg_remap_restore()
78 dev->backup_l2 = 0; in mt7925_reg_remap_restore()
119 { 0x830c0000, 0x000000, 0x0001000 }, /* WF_MCU_BUS_CR_REMAP */ in __mt7925_reg_addr()
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmmio.c20 #define INVALID_REG_ADDR 0xffffffff
23 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
24 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
25 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
26 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
27 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
28 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
29 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
30 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
31 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
[all …]
/linux/drivers/net/ethernet/qlogic/netxen/
H A Dnetxen_nic_hw.c16 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
18 #define MS_WIN(addr) (addr & 0x0ffc0000)
22 #define CRB_BLK(off) ((off >> 20) & 0x3f)
23 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
24 #define CRB_WINDOW_2M (0x130060)
25 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
26 #define CRB_INDIRECT_2M (0x1e0000UL)
57 {{{0, 0, 0, 0} } }, /* 0: PCI */
58 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
[all …]
/linux/drivers/scsi/qla4xxx/
H A Dql4_nx.c18 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
19 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
20 #define MS_WIN(addr) (addr & 0x0ffc0000)
21 #define QLA82XX_PCI_MN_2M (0)
22 #define QLA82XX_PCI_MS_2M (0x80000)
23 #define QLA82XX_PCI_OCM0_2M (0xc0000)
24 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
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