Home
last modified time | relevance | path

Searched +full:0 +full:x11c00000 (Results 1 – 22 of 22) sorted by relevance

/freebsd/sys/contrib/device-tree/Bindings/display/samsung/
H A Dsamsung,fimd.yaml65 default: 0
78 default: 0
85 default: 0
130 const: 0
133 "^port@[0-4]+$":
137 0 - for CAMIF0 input,
172 reg = <0x11c00000 0x20000>;
174 interrupts = <11 0>, <11 1>, <11 2>;
182 #size-cells = <0>;
187 pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
/freebsd/sys/contrib/device-tree/Bindings/display/exynos/
H A Dsamsung-fimd.txt27 - pinctrl-0: pin control group to be used for this controller.
48 If not specified, the default value(0) will be used.
51 If not specified, the default value(0) will be used.
56 If not specified, the default value(0) will be used.
76 0 - for CAMIF0 input,
92 reg = <0x11c00000 0x20000>;
94 interrupts = <11 0>, <11 1>, <11 2>;
104 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dmediatek,mt8188-pinctrl.yaml188 reg = <0x10005000 0x1000>,
189 <0x11c00000 0x1000>,
190 <0x11e10000 0x1000>,
191 <0x11e20000 0x1000>,
192 <0x11ea0000 0x1000>,
193 <0x1000b000 0x1000>;
199 gpio-ranges = <&pio 0 0 176>;
201 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH 0>;
H A Dmediatek,mt7981-pinctrl.yaml85 "wa_aice1" "wa_aice" 0, 1
86 "wa_aice2" "wa_aice" 0, 1
87 "wm_uart_0" "uart" 0, 1
88 "dfd" "dfd" 0, 1, 4, 5
388 Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
391 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
392 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
393 2: (R1, R0) = (1, 0) whic
[all...]
/freebsd/contrib/llvm-project/llvm/lib/ExecutionEngine/RuntimeDyld/Targets/
H A DRuntimeDyldMachOAArch64.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
38 int64_t Addend = 0; in decodeAddend()
71 assert((((uintptr_t)LocalAddress & 0x3) == 0) && in decodeAddend()
90 assert(((*p & 0xFC000000) == 0x14000000 || in decodeAddend()
91 (*p & 0xFC000000) == 0x94000000) && in decodeAddend()
97 Addend = (*p & 0x03FFFFFF) << 2; in decodeAddend()
105 assert((*p & 0x9F000000) == 0x90000000 && "Expected adrp instruction."); in decodeAddend()
110 Addend = ((*p & 0x60000000) >> 29) | ((*p & 0x01FFFFE0) >> 3) << 12; in decodeAddend()
119 assert((*p & 0x3B000000) == 0x39000000 && in decodeAddend()
127 assert((((*p & 0x3B000000) == 0x39000000) || in decodeAddend()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7981b.dtsi15 #size-cells = <0>;
17 cpu@0 {
19 reg = <0x0>;
26 reg = <0x1>;
36 #clock-cells = <0>;
52 reg = <0 0x0c000000 0 0x40000>, /* GICD */
53 <0 0x0c080000 0 0x200000>; /* GICR */
62 reg = <0 0x10001000 0 0x1000>;
68 reg = <0 0x1001b000 0 0x1000>;
74 reg = <0 0x1001c000 0 0x1000>;
[all …]
H A Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
H A Dmt8365.dtsi38 #size-cells = <0>;
40 cluster0_opp: opp-table-0 {
142 cpu0: cpu@0 {
145 reg = <0x0>;
149 i-cache-size = <0x8000>;
152 d-cache-size = <0x8000>;
165 reg = <0x1>;
169 i-cache-size = <0x8000>;
172 d-cache-size = <0x8000>;
185 reg = <0x2>;
[all …]
H A Dmt8188.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0x000>;
78 performance-domains = <&performance 0>;
85 reg = <0x100>;
97 performance-domains = <&performance 0>;
104 reg = <0x200>;
116 performance-domains = <&performance 0>;
123 reg = <0x300>;
135 performance-domains = <&performance 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos2200.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
92 cpu0: cpu@0 {
95 reg = <0>;
105 reg = <0x100>;
115 reg = <0x200>;
125 reg = <0x300>;
135 reg = <0x400>;
[all …]
H A Dexynos850.dtsi52 #clock-cells = <0>;
57 #size-cells = <0>;
91 cpu0: cpu@0 {
94 reg = <0x0>;
102 reg = <0x1>;
108 reg = <0x2>;
114 reg = <0x3>;
120 reg = <0x100>;
128 reg = <0x101>;
134 reg = <0x102>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/renesas/
H A Dr9a08g045.dtsi19 #clock-cells = <0>;
21 clock-frequency = <0>;
26 #clock-cells = <0>;
28 clock-frequency = <0>;
31 cluster0_opp: opp-table-0 {
60 #size-cells = <0>;
62 cpu0: cpu@0 {
64 reg = <0>;
73 L3_CA55: cache-controller-0 {
77 cache-size = <0x40000>;
[all …]
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos3250.dtsi199 #size-cells = <0>;
212 cpu0: cpu@0 {
215 reg = <0>;
259 xusbxti: clock-0 {
261 clock-frequency = <0>;
262 #clock-cells = <0>;
268 clock-frequency = <0>;
269 #clock-cells = <0>;
275 clock-frequency = <0>;
276 #clock-cells = <0>;
[all …]
H A Dexynos4.dtsi68 reg = <0x03810000 0x0c>;
79 reg = <0x03830000 0x100>;
88 samsung,idma-addr = <0x03000000>;
95 reg = <0x10000000 0x100>;
100 reg = <0x10500000 0x2000>;
105 reg = <0x12570000 0x14>;
110 reg = <0x10023c40 0x20>;
111 #power-domain-cells = <0>;
117 reg = <0x10023c60 0x20>;
118 #power-domain-cells = <0>;
[all …]
H A Dexynos5250.dtsi47 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
80 cpu0_opp_table: opp-table-0 {
176 reg = <0x02020000 0x30000>;
179 ranges = <0 0x02020000 0x30000>;
181 smp-sram@0 {
183 reg = <0x0 0x1000>;
188 reg = <0x2f000 0x1000>;
194 reg = <0x10044000 0x20>;
[all …]
H A Dexynos5420.dtsi153 cluster_a15_opp_table: opp-table-0 {
270 reg = <0x10d20000 0x1000>;
271 ranges = <0x0 0x10d20000 0x6000>;
276 reg = <0x4000 0x1000>;
281 reg = <0x5000 0x1000>;
287 reg = <0x10010000 0x30000>;
293 reg = <0x03810000 0x0c>;
303 reg = <0x11000000 0x10000>;
316 #size-cells = <0>;
317 reg = <0x12200000 0x2000>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMask.h3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
17 0xf0000000,
18 0xb0000000,
19 0x0fe03fe0,
20 0 },
23 0xffc00000,
24 0x76000000,
25 0x00203fe0,
26 0 },
29 0xff800000,
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]