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/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dmtk-sd.txt31 - pinctrl-0: should contain default/high speed pin ctrl
42 The value is an integer from 0 to 31.
45 The value is an integer from 0 to 31.
51 Valid range = [0:0x7]. if not present, default value is 0.
59 reg = <0 0x11230000 0 0x108>;
67 pinctrl-0 = <&mmc0_pins_default>;
71 hs400-ds-delay = <0x14015>;
H A Dmtk-sd.yaml79 pinctrl-0:
98 minimum: 0
99 maximum: 0xffffffff
106 The value is an integer from 0 to 31.
107 minimum: 0
115 The value is an integer from 0 to 31.
116 minimum: 0
130 pad macro, there are 32 stages from 0 to 31.
135 minimum: 0
142 data crc error caused by stop clock(fifo full) Valid range = [0
[all...]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmediatek-pcie-gen3.yaml27 |0|1|2|3|4|5|6|7| (PCIe intc)
34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
76 const: 0
120 const: 0
264 reg = <0x00 0x11230000 0x00 0x4000>;
266 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
267 bus-range = <0x00 0xff>;
268 ranges = <0x82000000 0x00 0x12000000 0x00
269 0x12000000 0x00 0x1000000>;
289 interrupt-map-mask = <0 0 0 0x7>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986a.dtsi21 #size-cells = <0>;
22 cpu0: cpu@0 {
24 reg = <0x0>;
32 reg = <0x1>;
40 reg = <0x2>;
48 reg = <0x3>;
58 #clock-cells = <0>;
73 reg = <0 0x43000000 0 0x30000>;
79 reg = <0 0x4fc00000 0 0x00100000>;
83 reg = <0 0x4fd00000 0 0x40000>;
[all …]
H A Dmt6795.dtsi48 #size-cells = <0>;
50 cpu0: cpu@0 {
54 reg = <0x000>;
63 reg = <0x001>;
78 reg = <0x002>;
93 reg = <0x003>;
108 reg = <0x100>;
123 reg = <0x101>;
138 reg = <0x102>;
153 reg = <0x10
[all...]
H A Dmt8365.dtsi24 #size-cells = <0>;
26 cluster0_opp: opp-table-0 {
128 cpu0: cpu@0 {
131 reg = <0x0>;
135 i-cache-size = <0x8000>;
138 d-cache-size = <0x8000>;
151 reg = <0x1>;
155 i-cache-size = <0x8000>;
158 d-cache-size = <0x8000>;
171 reg = <0x2>;
[all …]
H A Dmt7622.dtsi69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
140 reg = <0 0x43000000 0 0x30000>;
150 thermal-sensors = <&thermal 0>;
216 reg = <0 0x10000000 0 0x1000>;
223 reg = <0 0x10001000 0 0x250>;
[all …]
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
H A Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]
H A Dmt8188.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x000>;
50 reg = <0x100>;
68 reg = <0x200>;
86 reg = <0x300>;
104 reg = <0x400>;
122 reg = <0x500>;
140 reg = <0x600>;
158 reg = <0x700>;
[all …]
H A Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]
H A Dmt8183.dtsi293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
[all …]
H A Dmt8186.dtsi329 #size-cells = <0>;
367 cpu0: cpu@0 {
370 reg = <0x000>;
394 reg = <0x100>;
418 reg = <0x200>;
442 reg = <0x300>;
466 reg = <0x400>;
490 reg = <0x500>;
514 reg = <0x600>;
538 reg = <0x700>;
[all …]
H A Dmt8195.dtsi51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x000>;
58 performance-domains = <&performance 0>;
75 reg = <0x100>;
77 performance-domains = <&performance 0>;
94 reg = <0x200>;
96 performance-domains = <&performance 0>;
113 reg = <0x300>;
115 performance-domains = <&performance 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt7623.dtsi73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_dbg_values.h34 0x02, 0x00, 0x04, 0x00, 0x01, 0x09, 0x01, 0x08, 0x07, 0x02, 0x00, 0x01,
35 0x04, 0x05, 0x00, 0x01, 0x07, 0x09, 0x02, 0x00, 0x01, 0x04, 0x12, 0x00,
36 0x00, 0x06, 0x02, 0x00, 0x01, 0x04, 0x05, 0x00, 0x00, 0x06, 0x02, 0x00,
37 0x01, 0x05, 0x12, 0x00, 0x00, 0x06, 0x02, 0x00, 0x04, 0x00, 0x01, 0x09,
38 0x00, 0x06, 0x02, 0x00, 0x04, 0x02, 0x00, 0x0b, 0x0e, 0x00, 0x01, 0x00,
39 0x06, 0x01, 0x04, 0x05, 0x02, 0x00, 0x12, 0x00, 0x01, 0x07, 0x09, 0x02,
40 0x00, 0x04, 0x00, 0x01, 0x08, 0x07, 0x02, 0x00, 0x04, 0x00, 0x01, 0x07,
41 0x09, 0x02, 0x00, 0x04, 0x02, 0x00, 0x0b, 0x10, 0x02, 0x00, 0x04, 0x02,
42 0x00, 0x0b, 0x0f, 0x02, 0x04, 0x00, 0x01, 0x07, 0x09, 0x02, 0x00, 0x04,
43 0x02, 0x0b, 0x0e, 0x02, 0x00, 0x04, 0x00, 0x00, 0x06, 0x02, 0x04, 0x02,
[all …]
/freebsd/tools/test/iconv/ref/
H A DUTF-32BE-rev1 0x00 = 0x00000000
2 0x01 = 0x01000000
3 0x02 = 0x02000000
4 0x03 = 0x03000000
5 0x04 = 0x04000000
6 0x05 = 0x05000000
7 0x06 = 0x06000000
8 0x07 = 0x07000000
9 0x08 = 0x08000000
10 0x09 = 0x09000000
[all …]