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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drenesas,rzg3e-xspi.yaml89 "flash@[0-9a-f]+$":
121 reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
126 clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
127 <&cpg CPG_CORE 9>, <&cpg CPG_MOD 0xa1>;
130 resets = <&cpg 0xa3>, <&cpg 0xa4>;
133 #size-cells = <0>;
135 flash@0 {
137 reg = <0>;
/linux/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzg2l-pinctrl.yaml62 E.g. "interrupts = <RZG2L_GPIO(43, 0) IRQ_TYPE_EDGE_FALLING>;" if P43_0 is
134 enum: [0, 1, 2, 3]
138 $ref: "#/additionalProperties/anyOf/0"
179 reg = <0x11030000 0x10000>;
183 gpio-ranges = <&pinctrl 0 0 392>;
193 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
204 gpios = <RZG2L_GPIO(39, 2) 0>;
211 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi30 #size-cells = <0>;
35 reg = <0xf00>;
46 reg = <0xf01>;
56 reg = <0xf02>;
66 reg = <0xf03>;
74 cpu0_opp_table: opp-table-0 {
130 #clock-cells = <0>;
140 reg = <0x100b0000 0x4000>;
147 pinctrl-0 = <&i2s1_bus>;
153 reg = <0x100c0000 0x4000>;
[all …]