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/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,sparx5-switch.yaml35 pattern: "^switch@[0-9a-f]+$"
103 const: 0
106 "^port@[0-9a-f]+$":
131 minimum: 0
138 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
140 enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
141 default: 0
147 3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable
149 enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]
150 default: 0
[all …]
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi28 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0x0>;
49 reg = <0x1>;
81 #clock-cells = <0>;
89 reg = <0x6 0x1110000c 0x24>;
94 #clock-cells = <0>;
100 #clock-cells = <0>;
116 reg = <0x6 0x00300000 0x10000>, /* GIC Dist */
117 <0x6 0x00340000 0xc0000>, /* GICR */
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
H A Dmt8173.dtsi53 cluster0_opp: opp-table-0 {
129 #size-cells = <0>;
151 cpu0: cpu@0 {
154 reg = <0x000>;
169 reg = <0x001>;
184 reg = <0x100>;
199 reg = <0x101>;
214 CPU_SLEEP_0: cpu-sleep-0 {
220 arm,psci-suspend-param = <0x0010000>;
242 cpu_suspend = <0x84000001>;
[all …]
H A Dmt8192.dtsi36 #clock-cells = <0>;
45 #clock-cells = <0>;
52 #clock-cells = <0>;
59 #size-cells = <0>;
61 cpu0: cpu@0 {
64 reg = <0x000>;
75 performance-domains = <&performance 0>;
83 reg = <0x100>;
94 performance-domains = <&performance 0>;
102 reg = <0x200>;
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi30 #size-cells = <0>;
35 reg = <0xf00>;
46 reg = <0xf01>;
56 reg = <0xf02>;
66 reg = <0xf03>;
74 cpu0_opp_table: opp-table-0 {
130 #clock-cells = <0>;
140 reg = <0x100b0000 0x4000>;
147 pinctrl-0 = <&i2s1_bus>;
153 reg = <0x100c0000 0x4000>;
[all …]