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/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-mediatek.txt29 - pinctrl-0: One property must exist for each entry in pinctrl-names.
39 reg = <0 0x11006000 0 0x1000>;
51 pinctrl-0 = <&pwm0_pins>;
H A Dmediatek,mt2712-pwm.yaml82 reg = <0x11006000 0x1000>;
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dmtk-uart.txt32 index 0: an interrupt specifier for the UART controller itself
51 reg = <0x11006000 0x400>;
57 pinctrl-0 = <&uart_pin>;
H A Dmediatek,uart.yaml92 pinctrl-0: true
115 reg = <0x11006000 0x400>;
121 pinctrl-0 = <&uart_pin>;
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt6580.dtsi19 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
29 reg = <0x1>;
34 reg = <0x2>;
39 reg = <0x3>;
47 #clock-cells = <0>;
53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x10008000 0x80>;
[all …]
H A Dmt6589.dtsi19 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
30 reg = <0x1>;
35 reg = <0x2>;
40 reg = <0x3>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
78 reg = <0x10008000 0x80>;
[all …]
H A Dmt8135.dtsi42 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x000>;
54 reg = <0x001>;
60 reg = <0x100>;
66 reg = <0x101>;
77 reg = <0 0x80002000 0 0x1000>;
90 #clock-cells = <0>;
96 #clock-cells = <0>;
101 #clock-cells = <0>;
[all …]
H A Dmt7629.dtsi24 #size-cells = <0>;
27 cpu0: cpu@0 {
30 reg = <0x0>;
38 reg = <0x1>;
51 clk20m: oscillator-0 {
53 #clock-cells = <0>;
60 #clock-cells = <0>;
83 reg = <0x10000000 0x1000>;
89 reg = <0x10002000 0x1000>;
97 reg = <0x10006000 0x1000>;
[all …]
H A Dmt7623.dtsi73 #size-cells = <0>;
76 cpu0: cpu@0 {
79 reg = <0x0>;
91 reg = <0x1>;
103 reg = <0x2>;
115 reg = <0x3>;
137 #clock-cells = <0>;
142 #clock-cells = <0>;
147 clk26m: oscillator-0 {
149 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8516.dtsi21 cluster0_opp: opp-table-0 {
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
105 CPU_SLEEP_0_0: cpu-sleep-0-0 {
110 arm,psci-suspend-param = <0x0010000>;
113 CLUSTER_SLEEP_0: cluster-sleep-0 {
[all …]
H A Dmt6795.dtsi48 #size-cells = <0>;
50 cpu0: cpu@0 {
54 reg = <0x000>;
63 reg = <0x001>;
78 reg = <0x002>;
93 reg = <0x003>;
108 reg = <0x100>;
123 reg = <0x101>;
138 reg = <0x102>;
153 reg = <0x10
[all...]
H A Dmt8365.dtsi24 #size-cells = <0>;
26 cluster0_opp: opp-table-0 {
128 cpu0: cpu@0 {
131 reg = <0x0>;
135 i-cache-size = <0x8000>;
138 d-cache-size = <0x8000>;
151 reg = <0x1>;
155 i-cache-size = <0x8000>;
158 d-cache-size = <0x8000>;
171 reg = <0x2>;
[all …]
H A Dmt7622.dtsi69 #size-cells = <0>;
71 cpu0: cpu@0 {
74 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
140 reg = <0 0x43000000 0 0x30000>;
150 thermal-sensors = <&thermal 0>;
216 reg = <0 0x10000000 0 0x1000>;
223 reg = <0 0x10001000 0 0x250>;
[all …]
H A Dmt2712e.dtsi22 cluster0_opp: opp-table-0 {
66 #size-cells = <0>;
85 cpu0: cpu@0 {
88 reg = <0x000>;
100 reg = <0x001>;
113 reg = <0x200>;
126 CPU_SLEEP_0: cpu-sleep-0 {
132 arm,psci-suspend-param = <0x0010000>;
135 CLUSTER_SLEEP_0: cluster-sleep-0 {
141 arm,psci-suspend-param = <0x1010000>;
[all …]
H A Dmt8183.dtsi293 #size-cells = <0>;
327 cpu0: cpu@0 {
330 reg = <0x000>;
353 reg = <0x001>;
376 reg = <0x002>;
399 reg = <0x003>;
422 reg = <0x100>;
445 reg = <0x101>;
468 reg = <0x102>;
491 reg = <0x103>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/exynos/
H A Dexynos7.dtsi44 #clock-cells = <0>;
49 #size-cells = <0>;
51 cpu_atlas0: cpu@0 {
54 reg = <0x0>;
56 i-cache-size = <0xc000>;
59 d-cache-size = <0x8000>;
68 reg = <0x1>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
82 reg = <0x
[all...]
H A Dexynos5433.dtsi48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]