Searched +full:0 +full:x10a00000 (Results 1 – 6 of 6) sorted by relevance
19 reg = <0x0 0x08000000>;23 #address-cells = <0>;33 reg = <0x10200000 0x10000>;34 xlnx,kind-of-intr = <0x0>;35 xlnx,num-intr-inputs = <0x6>;45 reg = <0x10600000 0x10000>;46 xlnx,all-inputs = <0x0>;47 xlnx,dout-default = <0x0>;48 xlnx,gpio-width = <0x16>;49 xlnx,interrupt-present = <0x0>;[all …]
74 - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)75 - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)149 reg = <0x10a00000 0x8000>;
201 reg = <0x7f005000 0x100>;217 reg = <0x10a00000 0xc0>;221 interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>;222 pinctrl-0 = <&uart0_bus>;
35 #size-cells = <0>;63 cpu0: cpu@0 {66 reg = <0x0>;73 reg = <0x1>;80 reg = <0x100>;87 reg = <0x101>;94 reg = <0x102>;101 reg = <0x103>;114 reg = <0x10010000 0x10000>;128 reg = <0x10200000 0x10000>;[all …]
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300108 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */116 #define AU1000_USB_OHCI_PHYS_ADDR 0x10100000 /* 012 */[all …]
28 /* Register Offset definitions for CMU_TOP (0x1a330000) */29 #define PLL_LOCKTIME_PLL_G3D 0x000030 #define PLL_LOCKTIME_PLL_MMC 0x000431 #define PLL_LOCKTIME_PLL_SHARED0 0x000832 #define PLL_LOCKTIME_PLL_SHARED1 0x000c33 #define PLL_LOCKTIME_PLL_SHARED2 0x001034 #define PLL_LOCKTIME_PLL_SHARED3 0x001435 #define PLL_LOCKTIME_PLL_SHARED4 0x001836 #define PLL_CON0_PLL_G3D 0x010037 #define PLL_CON3_PLL_G3D 0x010c[all …]