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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rzv2h-cpg.yaml49 calculation is (1 * 16 + 3) = 0x13.
53 const: 0
60 for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30.
78 reg = <0x10420000 0x10000>;
82 #power-domain-cells = <0>;
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g056.dtsi12 /* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
13 #define RZV2N_P0 0
36 #clock-cells = <0>;
38 clock-frequency = <0>;
48 cluster0_opp: opp-table-0 {
76 #size-cells = <0>;
78 cpu0: cpu@0 {
80 reg = <0>;
90 reg = <0x100>;
100 reg = <0x200>;
[all …]
H A Dr9a09g047.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
58 #size-cells = <0>;
60 cpu0: cpu@0 {
62 reg = <0>;
72 reg = <0x100>;
82 reg = <0x200>;
92 reg = <0x300>;
100 L3_CA55: cache-controller-0 {
[all …]
H A Dr9a09g057.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
30 cluster0_opp: opp-table-0 {
58 #size-cells = <0>;
60 cpu0: cpu@0 {
62 reg = <0>;
72 reg = <0x100>;
82 reg = <0x200>;
92 reg = <0x300>;
100 L3_CA55: cache-controller-0 {
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos8895.dtsi31 #size-cells = <0>;
65 cpu4: cpu@0 {
68 reg = <0x0>;
75 reg = <0x1>;
82 reg = <0x2>;
89 reg = <0x3>;
96 reg = <0x100>;
103 reg = <0x101>;
110 reg = <0x102>;
117 reg = <0x103>;
[all …]
/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
[all …]