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/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_phy.c36 for (i = 0; i < 8; i += 2) { in hdmi_phy_parse_lanes()
43 if (dx < 0 || dx >= 8) in hdmi_phy_parse_lanes()
46 if (dy < 0 || dy >= 8) in hdmi_phy_parse_lanes()
56 pol = 0; in hdmi_phy_parse_lanes()
65 return 0; in hdmi_phy_parse_lanes()
71 0x0123, in hdmi_phy_configure_lanes()
72 0x0132, in hdmi_phy_configure_lanes()
73 0x0312, in hdmi_phy_configure_lanes()
74 0x0321, in hdmi_phy_configure_lanes()
75 0x0231, in hdmi_phy_configure_lanes()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_phy.c45 for (i = 0; i < 8; i += 2) { in hdmi_phy_parse_lanes()
52 if (dx < 0 || dx >= 8) in hdmi_phy_parse_lanes()
55 if (dy < 0 || dy >= 8) in hdmi_phy_parse_lanes()
65 pol = 0; in hdmi_phy_parse_lanes()
74 return 0; in hdmi_phy_parse_lanes()
80 0x0123, in hdmi_phy_configure_lanes()
81 0x0132, in hdmi_phy_configure_lanes()
82 0x0312, in hdmi_phy_configure_lanes()
83 0x0321, in hdmi_phy_configure_lanes()
84 0x0231, in hdmi_phy_configure_lanes()
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml78 const: 0
81 "^dai-link@[0-9a-f]+$":
254 reg = <0 0x62d87000 0 0x68000>,
255 <0 0x62f00000 0 0x29000>;
258 iommus = <&apps_smmu 0x1020 0>,
259 <&apps_smmu 0x1032 0>;
260 power-domains = <&lpass_hm 0>;
273 interrupts = <0 160 1>,
274 <0 268 1>;
280 #size-cells = <0>;
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dsmt_p.h19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
/linux/drivers/mtd/devices/
H A Ddocg3.h15 * - 0x0000 .. 0x07ff : IPL
16 * - 0x0800 .. 0x0fff : Data area
17 * - 0x1000 .. 0x17ff : Registers
18 * - 0x1800 .. 0x1fff : Unknown
20 #define DOC_IOSPACE_IPL 0x0000
21 #define DOC_IOSPACE_DATA 0x0800
22 #define DOC_IOSPACE_SIZE 0x2000
30 #define DOC_ADDR_PAGE_MASK 0x3f
48 #define DOC_ECC_BCH_PRIMPOLY 0x4443
59 #define DOC_LAYOUT_BLOCK_BBT 0
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/linux/arch/sh/include/asm/
H A Dhd64461.h10 * (please note manual reference 0x10000000 = 0xb0000000)
14 #define HD64461_PCC_WINDOW 0x01000000
16 /* Area 6 - Slot 0 - memory and/or IO card */
17 #define HD64461_IOBASE 0xb0000000
19 #define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
20 #define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
21 #define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
22 #define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
25 #define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
26 #define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
[all …]
/linux/drivers/gpu/drm/bridge/synopsys/
H A Ddw-hdmi.h10 #define HDMI_DESIGN_ID 0x0000
11 #define HDMI_REVISION_ID 0x0001
12 #define HDMI_PRODUCT_ID0 0x0002
13 #define HDMI_PRODUCT_ID1 0x0003
14 #define HDMI_CONFIG0_ID 0x0004
15 #define HDMI_CONFIG1_ID 0x0005
16 #define HDMI_CONFIG2_ID 0x0006
17 #define HDMI_CONFIG3_ID 0x0007
20 #define HDMI_IH_FC_STAT0 0x0100
21 #define HDMI_IH_FC_STAT1 0x0101
[all …]
/linux/drivers/usb/misc/
H A Dldusb.c33 #define USB_VENDOR_ID_LD 0x0f11 /* USB Vendor ID of LD Didactic GmbH */
34 #define USB_DEVICE_ID_LD_CASSY 0x1000 /* USB Product ID of CASSY-S modules with 8 bytes endpoint s…
35 #define USB_DEVICE_ID_LD_CASSY2 0x1001 /* USB Product ID of CASSY-S modules with 64 bytes endpoint…
36 #define USB_DEVICE_ID_LD_POCKETCASSY 0x1010 /* USB Product ID of Pocket-CASSY */
37 #define USB_DEVICE_ID_LD_POCKETCASSY2 0x1011 /* USB Product ID of Pocket-CASSY 2 (reserved) */
38 #define USB_DEVICE_ID_LD_MOBILECASSY 0x1020 /* USB Product ID of Mobile-CASSY */
39 #define USB_DEVICE_ID_LD_MOBILECASSY2 0x1021 /* USB Product ID of Mobile-CASSY 2 (reserved) */
40 #define USB_DEVICE_ID_LD_MICROCASSYVOLTAGE 0x1031 /* USB Product ID of Micro-CASSY Voltage */
41 #define USB_DEVICE_ID_LD_MICROCASSYCURRENT 0x1032 /* USB Product ID of Micro-CASSY Current */
42 #define USB_DEVICE_ID_LD_MICROCASSYTIME 0x1033 /* USB Product ID of Micro-CASSY Time (reserved) */
[all …]
/linux/drivers/staging/rtl8723bs/hal/
H A Dsdio_ops.c60 case 0x1025: in get_deviceid()
64 case 0x1026: in get_deviceid()
68 case 0x1031: in get_deviceid()
72 case 0x1032: in get_deviceid()
76 case 0x1033: in get_deviceid()
80 case 0x1034: in get_deviceid()
99 offset = 0; in _cvrt2ftaddr()
168 ((device_id == WLAN_IOREG_DEVICE_ID) && (offset < 0x100)) || in sdio_read32()
177 shift = ftaddr & 0x3; in sdio_read32()
178 if (shift == 0) { in sdio_read32()
[all …]
/linux/drivers/hid/
H A Dhid-ids.h17 #define USB_VENDOR_ID_258A 0x258a
18 #define USB_DEVICE_ID_258A_6A88 0x6a88
20 #define USB_VENDOR_ID_3M 0x0596
21 #define USB_DEVICE_ID_3M1968 0x0500
22 #define USB_DEVICE_ID_3M2256 0x0502
23 #define USB_DEVICE_ID_3M3266 0x0506
25 #define USB_VENDOR_ID_A4TECH 0x09da
26 #define USB_DEVICE_ID_A4TECH_WCP32PU 0x0006
27 #define USB_DEVICE_ID_A4TECH_X5_005D 0x000a
28 #define USB_DEVICE_ID_A4TECH_RP_649 0x001a
[all …]
H A Dhid-lg.c29 #define LG_RDESC 0x001
30 #define LG_BAD_RELATIVE_KEYS 0x002
31 #define LG_DUPLICATE_USAGES 0x004
32 #define LG_EXPANDED_KEYMAP 0x010
33 #define LG_IGNORE_DOUBLED_WHEEL 0x020
34 #define LG_WIRELESS 0x040
35 #define LG_INVERT_HWHEEL 0x080
36 #define LG_NOGET 0x100
37 #define LG_FF 0x200
38 #define LG_FF2 0x400
[all …]
/linux/drivers/net/fddi/
H A Ddefxx.h70 #define PI_ALIGN_K_XMT_DATA_BUFF 0 /* Xmt data que buffer alignment */
75 #define PI_PHY_K_S 0 /* Index to S phy */
76 #define PI_PHY_K_A 0 /* Index to A phy */
95 #define PI_FMC_DESCR_V_LEN 0
97 #define PI_FMC_DESCR_M_SOP 0x80000000
98 #define PI_FMC_DESCR_M_EOP 0x40000000
99 #define PI_FMC_DESCR_M_FSC 0x38000000
100 #define PI_FMC_DESCR_M_FSB_ERROR 0x04000000
101 #define PI_FMC_DESCR_M_FSB_ADDR_RECOG 0x02000000
102 #define PI_FMC_DESCR_M_FSB_ADDR_COPIED 0x01000000
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/linux/include/linux/
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/linux/sound/usb/
H A Dquirks-table.h117 USB_DEVICE(0x0403, 0xb8d8),
121 .ifnum = 0,
128 USB_DEVICE(0x041e, 0x0005),
136 .endpoint = 0x03,
138 .attributes = 0,
147 { USB_DEVICE_VENDOR_SPEC(0x041e, 0x3f02) },
149 { USB_DEVICE_VENDOR_SPEC(0x041e, 0x3f04) },
151 { USB_DEVICE_VENDOR_SPEC(0x041e, 0x3f0a) },
153 { USB_DEVICE_VENDOR_SPEC(0x041e, 0x3f19) },
155 { USB_DEVICE_VENDOR_SPEC(0x31b2, 0x0011) },
[all …]
/linux/drivers/net/ethernet/intel/
H A De100.c86 * hardware will not write to a size 0 descriptor and mark the previous
170 static int eeprom_bad_csum_allow = 0;
171 static int use_io = 0;
172 module_param(debug, int, 0);
175 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
181 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
183 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
184 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
185 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
186 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
[all …]
/linux/drivers/net/ethernet/marvell/
H A Dskge.c56 #define SKGE_EEPROM_MAGIC 0x9933aabb
69 module_param(debug, int, 0);
70 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_offset.h27 // base address: 0x0
28 …PHYPLLA_PIXCLK_RESYNC_CNTL 0x0040
30 …PHYPLLB_PIXCLK_RESYNC_CNTL 0x0041
32 …DP_DTO_DBUF_EN 0x0044
34 …DPREFCLK_CGTT_BLK_CTRL_REG 0x0048
36 …REFCLK_CNTL 0x0049
38 …REFCLK_CGTT_BLK_CTRL_REG 0x004b
40 …DCCG_PERFMON_CNTL2 0x004e
42 …DCCG_DS_DTO_INCR 0x0053
44 …DCCG_DS_DTO_MODULO 0x0054
[all …]
/linux/sound/soc/codecs/
H A Dwm8962.h16 #define WM8962_SYSCLK_MCLK 0
30 #define WM8962_LEFT_INPUT_VOLUME 0x00
31 #define WM8962_RIGHT_INPUT_VOLUME 0x01
32 #define WM8962_HPOUTL_VOLUME 0x02
33 #define WM8962_HPOUTR_VOLUME 0x03
34 #define WM8962_CLOCKING1 0x04
35 #define WM8962_ADC_DAC_CONTROL_1 0x05
36 #define WM8962_ADC_DAC_CONTROL_2 0x06
37 #define WM8962_AUDIO_INTERFACE_0 0x07
38 #define WM8962_CLOCKING2 0x08
[all …]
/linux/lib/
H A Dtest_bpf.c26 #define MAX_K 0xffffFFFF
30 #define SKB_MARK 0x1234aaaa
31 #define SKB_HASH 0x1234aaab
33 #define SKB_VLAN_TCI 0xffff
52 #define FLAG_NO_DATA BIT(0)
85 int nr_testruns; /* Custom run count, defaults to MAX_TESTRUNS if 0 */
94 __u32 k = ~0; in bpf_fill_maxinsns1()
101 for (i = 0; i < len; i++, k--) in bpf_fill_maxinsns1()
107 return 0; in bpf_fill_maxinsns1()
120 for (i = 0; i < len; i++) in bpf_fill_maxinsns2()
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_1_offset.h24 …SQ_DEBUG_STS_GLOBAL 0x0309
25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0
26 …SQ_DEBUG_STS_GLOBAL2 0x0310
27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0
28 …SQ_DEBUG_STS_GLOBAL3 0x0311
29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0
32 // base address: 0x8000
33 …GRBM_CNTL 0x0000
34 …ne mmGRBM_CNTL_BASE_IDX 0
35 …GRBM_SKEW_CNTL 0x0001
[all …]

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