Searched +full:0 +full:x101d0000 (Results 1 – 7 of 7) sorted by relevance
108 enum: [0, 1, 2]127 reg = <0x101D0000 0x100>;128 interrupts = <0 42 0>;
42 <7 0>,60 reg = <0x02020000 0x54000>;63 ranges = <0 0x02020000 0x54000>;65 smp-sram@0 {67 reg = <0x0 0x1000>;72 reg = <0x53000 0x1000>;79 reg = <0x101c0000 0xb00>;96 reg = <0x101d0000 0x100>;102 reg = <0x12d10000 0x100>;111 reg = <0x12ca0000 0x1000>;[all …]
47 #size-cells = <0>;60 cpu0: cpu@0 {63 reg = <0>;80 cpu0_opp_table: opp-table-0 {176 reg = <0x02020000 0x30000>;179 ranges = <0 0x02020000 0x30000>;181 smp-sram@0 {183 reg = <0x0 0x1000>;188 reg = <0x2f000 0x1000>;194 reg = <0x10044000 0x20>;[all …]
44 #clock-cells = <0>;49 #size-cells = <0>;51 cpu_atlas0: cpu@0 {54 reg = <0x0>;56 i-cache-size = <0xc000>;59 d-cache-size = <0x8000>;68 reg = <0x1>;70 i-cache-size = <0xc000>;73 d-cache-size = <0x8000>;82 reg = <0x[all...]
38 #clock-cells = <0>;44 #size-cells = <0>;87 cpu0: cpu@0 {90 reg = <0x0 0x0>;92 i-cache-size = <0x10000>;95 d-cache-size = <0x10000>;104 reg = <0x0 0x100>;106 i-cache-size = <0x10000>;109 d-cache-size = <0x10000>;118 reg = <0x0 0x200>;[all …]
59 * special values defined in the document, they are of the form 0xLTTTNNNN,63 * 0: static configuration100 #define TLV_TAG_END (0xEEEEEEEE)105 #define TLV_TAG_SKIP (0x00000000)106 #define TLV_TAG_INVALID (0xFFFFFFFF)111 * 0.114 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)120 /* 0 indicates the default segment (always located at offset 0), while other values122 * The default segment may also have preset > 0, which means that it is a preset123 * selected through an RFID command and copied by FW to the location at offset 0. */[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]