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/freebsd/sys/contrib/device-tree/Bindings/soc/fsl/
H A Dbman-portals.txt44 ranges = <0 0xf 0xf4000000 0x200000>;
46 bman-portal@0 {
47 compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
48 reg = <0x0 0x4000>, <0x100000 0x1000>;
49 interrupts = <105 2 0 0>;
52 compatible = "fsl,bman-portal-1.0.0", "fsl,bman-portal";
53 reg = <0x4000 0x4000>, <0x101000 0x1000>;
54 interrupts = <107 2 0 0>;
H A Dqman-portals.txt92 ranges = <0 0xf 0xf4200000 0x200000>;
94 qman-portal@0 {
95 compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
96 reg = <0 0x4000>, <0x100000 0x1000>;
97 interrupts = <104 2 0 0>;
99 fsl,qman-channel-id = <0>;
102 fsl,liodn = <0x21>;
106 fsl,liodn = <0xa1>;
110 fsl,liodn = <0x41 0x66>;
115 compatible = "fsl,qman-portal-1.2.0", "fsl,qman-portal";
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp1023si-post.dtsi37 alloc-ranges = <0 0 0x10 0>;
42 alloc-ranges = <0 0 0x10 0>;
47 alloc-ranges = <0 0 0x10 0>;
54 interrupts = <19 2 0 0>,
55 <16 2 0 0>;
58 /* controller at 0xa000 */
64 bus-range = <0x0 0xff>;
66 interrupts = <16 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
[all …]
H A Dqoriq-dma-1.dtsi2 * QorIQ DMA device tree stub [ controller @ offset 0x101000 ]
39 reg = <0x101300 0x4>;
40 ranges = <0x0 0x101100 0x200>;
42 dma-channel@0 {
44 reg = <0x0 0x80>;
45 cell-index = <0>;
46 interrupts = <32 2 0 0>;
50 reg = <0x80 0x80>;
52 interrupts = <33 2 0 0>;
56 reg = <0x100 0x80>;
[all …]
H A Delo3-dma-1.dtsi2 * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
39 reg = <0x101300 0x4>,
40 <0x101600 0x4>;
41 ranges = <0x0 0x101100 0x500>;
42 dma-channel@0 {
44 reg = <0x0 0x80>;
45 interrupts = <32 2 0 0>;
49 reg = <0x80 0x80>;
50 interrupts = <33 2 0 0>;
54 reg = <0x100 0x80>;
[all …]
H A Dqoriq-bman1-portals.dtsi40 bman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <105 2 0 0>;
47 reg = <0x4000 0x4000>, <0x101000 0x1000>;
48 interrupts = <107 2 0 0>;
52 reg = <0x8000 0x4000>, <0x102000 0x1000>;
53 interrupts = <109 2 0 0>;
57 reg = <0xc000 0x4000>, <0x103000 0x1000>;
58 interrupts = <111 2 0 0>;
62 reg = <0x10000 0x4000>, <0x104000 0x1000>;
[all …]
H A Dqoriq-qman1-portals.dtsi40 qportal0: qman-portal@0 {
42 reg = <0x0 0x4000>, <0x100000 0x1000>;
43 interrupts = <104 2 0 0>;
44 cell-index = <0x0>;
48 reg = <0x4000 0x4000>, <0x101000 0x1000>;
49 interrupts = <106 2 0 0>;
54 reg = <0x8000 0x4000>, <0x102000 0x1000>;
55 interrupts = <108 2 0 0>;
60 reg = <0xc000 0x4000>, <0x103000 0x1000>;
61 interrupts = <110 2 0 0>;
[all …]
H A Dt1023si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
H A Dt1040si-post.dtsi39 alloc-ranges = <0 0 0x10000 0>;
44 alloc-ranges = <0 0 0x10000 0>;
49 alloc-ranges = <0 0 0x10000 0>;
56 interrupts = <25 2 0 0>;
64 bus-range = <0x0 0xff>;
65 interrupts = <20 2 0 0>;
67 pcie@0 {
68 reg = <0 0 0 0 0>;
73 interrupts = <20 2 0 0>;
74 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/lantiq/
H A Ddanube.dtsi8 cpu@0 {
17 reg = <0x1f800000 0x800000>;
18 ranges = <0x0 0x1f800000 0x7fffff>;
24 reg = <0x80200 0x120>;
29 reg = <0x803f0 0x10>;
37 reg = <0x1f000000 0x800000>;
38 ranges = <0x0 0x1f000000 0x7fffff>;
44 reg = <0x101000 0x1000>;
49 reg = <0x102000 0x1000>;
54 reg = <0x103000 0x1000>;
[all …]
/freebsd/sys/contrib/device-tree/src/mips/mscc/
H A Docelot.dtsi11 #size-cells = <0>;
13 cpu@0 {
17 reg = <0>;
26 #address-cells = <0>;
34 #clock-cells = <0>;
40 #clock-cells = <0>;
50 ranges = <0 0x70000000 0x2000000>;
54 cpu_ctrl: syscon@0 {
56 reg = <0x0 0x2c>;
61 reg = <0x70 0x70>;
[all …]
/freebsd/sys/dts/arm/
H A Dzynq-7000.dtsi36 memreserve = <0x00000000 0x00080000>;
45 ranges = <0x0 0xf8000000 0xf10000>;
50 reg = <0x0 0x1000>;
57 #address-cells = <0>;
59 reg = <0xf01000 0x1000>, // distributer registers
60 <0xf00100 0x0100>; // CPU if registers
66 reg = <0xf02000 0x1000>;
67 interrupts = <0 2 4>;
74 reg = <0x7000 0x1000>;
75 interrupts = <0 8 4>;
[all …]
/freebsd/sys/dts/powerpc/
H A Dp3041si.dtsi103 #size-cells = <0>;
105 cpu0: PowerPC,e500mc@0 {
107 reg = <0>;
145 dcsr-epu@0 {
147 interrupts = <52 2 0 0
148 84 2 0 0
149 85 2 0 0>;
151 reg = <0x0 0x1000>;
155 reg = <0x1000 0x1000 0x1000000 0x8000>;
159 reg = <0x2000 0x1000>;
[all …]
H A Dp2041si.dtsi102 #size-cells = <0>;
104 cpu0: PowerPC,e500mc@0 {
106 reg = <0>;
144 dcsr-epu@0 {
146 interrupts = <52 2 0 0
147 84 2 0 0
148 85 2 0 0>;
150 reg = <0x0 0x1000>;
154 reg = <0x1000 0x1000 0x1000000 0x8000>;
158 reg = <0x2000 0x1000>;
[all …]
H A Dp5020si.dtsi109 #size-cells = <0>;
111 cpu0: PowerPC,e5500@0 {
113 reg = <0>;
135 dcsr-epu@0 {
137 interrupts = <52 2 0 0
138 84 2 0 0
139 85 2 0 0>;
141 reg = <0x0 0x1000>;
145 reg = <0x1000 0x1000 0x1000000 0x8000>;
149 reg = <0x2000 0x1000>;
[all …]
/freebsd/sys/dev/bxe/
H A Decore_reg.h35 (0x1<<0)
37 (0x1<<2)
39 (0x1<<5)
41 (0x1<<3)
43 (0x1<<4)
45 (0x1<<1)
47 0x1100bcUL
49 0x1101c0UL
51 0x1101d8UL
53 0x1101d0UL
[all …]
H A Dbxe_dump.h33 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
34 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
35 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
36 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
56 #define BNX2X_DUMP_VERSION 0x61111111
76 static const uint32_t page_vals_e2[] = {0, 128};
79 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
85 static const uint32_t page_vals_e3[] = {0, 128};
88 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
92 { 0x2000, 1, 0x1f, 0xfff},
[all …]
H A D57711_init_values.c55 {OP_WR, 0x600dc, 0x1},
56 {OP_SW, 0x61000, 0x2000000},
57 {OP_RD, 0x600d8, 0x0},
58 {OP_SW, 0x60200, 0x30200},
59 {OP_WR, 0x600dc, 0x0},
62 {OP_RD, 0x600b8, 0x0},
63 {OP_RD, 0x600c8, 0x0},
64 {OP_WR, 0x6016c, 0x0},
67 {OP_RD, 0x600bc, 0x0},
68 {OP_RD, 0x600cc, 0x0},
[all …]
H A D57710_init_values.c55 {OP_WR, 0x600dc, 0x1},
56 {OP_SW, 0x61000, 0x2000000},
57 {OP_RD, 0x600d8, 0x0},
58 {OP_SW, 0x60200, 0x30200},
59 {OP_WR, 0x600dc, 0x0},
62 {OP_WR, 0x60068, 0xb8},
63 {OP_WR, 0x60078, 0x114},
64 {OP_RD, 0x600b8, 0x0},
65 {OP_RD, 0x600c8, 0x0},
68 {OP_WR, 0x6006c, 0xb8},
[all …]
H A D57712_init_values.c54 /* #define ATC_COMMON_START 0 */
55 {OP_WR, 0x1100b8, 0x1},
58 {OP_WR, 0x600dc, 0x1},
59 {OP_WR, 0x60050, 0x180},
60 {OP_SW, 0x61000, 0x1ff0000},
61 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
62 {OP_WR, 0x617fc, 0x3fe001},
63 {OP_IF_MODE_AND, 1, 0x10}, /* e3 */
64 {OP_SW, 0x617fc, 0x20101ff},
65 {OP_IF_MODE_AND, 1, 0x8}, /* e2 */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Decore_init_values.h35 0x00030003, 0xffff0000, /* if phase != 'engine', skip 3 ops (no DMAE) */
36 0x00020002, 0x00020000, /* if mode != '!asic', skip 2 ops */
37 0x0280c201, 0x00000000, /* write 0x0 to address 0x50184 */
38 0x02810201, 0x00000000, /* write 0x0 to address 0x50204 */
40 0x00110003, 0xffff0000, /* if phase != 'engine', skip 17 ops (no DMAE) */
41 0x00030002, 0x00020000, /* if mode != '!asic', skip 3 ops */
42 0x0048c201, 0x00000000, /* write 0x0 to address 0x9184 */
43 0x0048d201, 0x00000000, /* write 0x0 to address 0x91a4 */
44 0x004ba601, 0x00000001, /* write 0x1 to address 0x974c */
45 0x00020002, 0x00be0000, /* if mode != '(!asic)&bb', skip 2 ops */
[all …]