Searched +full:0 +full:x10080000 (Results 1 – 14 of 14) sorted by relevance
18 reg = <0x20 0x10020000 0 0x20000>;23 reg = <0x20 0x10080000 0 0x1000>;
18 cpu@0 {26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
18 cpu@0 {26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
159 reg = <0x5c000000 0x40000>; /* 256 KiB SRAM at address 0x5c000000 */163 ranges = <0 0x5c000000 0x40000>;166 reg = <0x100 0x50>;170 reg = <0x1000 0x1000>;175 reg = <0x20000 0x20000>;190 reg = <0x02020000 0x54000>;193 ranges = <0 0x02020000 0x54000>;195 smp-sram@0 {197 reg = <0x0 0x1000>;202 reg = <0x53000 0x1000>;[all …]
32 #clock-cells = <0>;38 #clock-cells = <0>;44 #clock-cells = <0>;51 reg = <0x20 0x10020000 0 0x20000>;58 #address-cells = <0>;60 reg = <0x20 0x01001000 0 0x1000>,61 <0x20 0x01002000 0 0x2000>,62 <0x20 0x01004000 0 0x2000>,63 <0x20 0x01006000 0 0x2000>;97 reg = <0x20 0x10030000 0 0x2000>;[all …]
23 #size-cells = <0>;26 cpu0: cpu@0 {30 reg = <0x0>;47 reg = <0x1>;74 reg = <0x10080000 0x10000>;77 ranges = <0 0x10080000 0x10000>;79 smp-sram@0 {81 reg = <0x0 0x50>;87 reg = <0x1010c000 0x19c>;102 #size-cells = <0>;[all …]
18 #size-cells = <0>;21 cpu0: cpu@0 {25 reg = <0x0>;35 reg = <0x1>;43 reg = <0x2>;51 reg = <0x3>;57 cpu0_opp_table: opp-table-0 {104 reg = <0x10080000 0x8000>;107 ranges = <0 0x10080000 0x8000>;109 smp-sram@0 {[all …]
37 #size-cells = <0>;43 reg = <0xf00>;56 reg = <0xf01>;87 #clock-cells = <0>;92 reg = <0x10080000 0x2000>;95 ranges = <0 0x10080000 0x2000>;97 smp-sram@0 {99 reg = <0x00 0x10>;105 reg = <0x10090000 0x10000>;125 reg = <0x10108000 0x800>;[all …]
29 #size-cells = <0>;34 reg = <0xf00>;43 cpu_opp_table: opp-table-0 {85 #clock-cells = <0>;90 reg = <0x10080000 0x2000>;93 ranges = <0 0x10080000 [all...]
44 #size-cells = <0>;50 reg = <0xf00>;61 reg = <0xf01>;69 reg = <0xf02>;77 reg = <0xf03>;83 cpu_opp_table: opp-table-0 {159 #clock-cells = <0>;164 reg = <0x10080000 0x2000>;167 ranges = <0 0x10080000 0x2000>;169 smp-sram@0 {[all …]
8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */9 0 0x20000000 0 0x2000000[all...]
59 * special values defined in the document, they are of the form 0xLTTTNNNN,63 * 0: static configuration100 #define TLV_TAG_END (0xEEEEEEEE)105 #define TLV_TAG_SKIP (0x00000000)106 #define TLV_TAG_INVALID (0xFFFFFFFF)111 * 0.114 #define TLV_TAG_PARTITION_HEADER (0xEF10DA7A)120 /* 0 indicates the default segment (always located at offset 0), while other values122 * The default segment may also have preset > 0, which means that it is a preset123 * selected through an RFID command and copied by FW to the location at offset 0. */[all …]
20 #size-cells = <0>;22 S7_0: cpu@0 {24 reg = <0>;200 cpu_opp: opp-table-0 {260 #clock-cells = <0>;265 #clock-cells = <0>;271 #clock-cells = <0>;277 #clock-cells = <0>;283 #clock-cells = <0>;289 #clock-cells = <0>;[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]