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/linux/Documentation/devicetree/bindings/sound/
H A Drenesas,rz-ssi.yaml65 bits[0:9] - Specifies MID/RID value of a SSI channel as below
66 MID/RID value of SSI rx0 = 0x256
67 MID/RID value of SSI tx0 = 0x255
68 MID/RID value of SSI rx1 = 0x25a
69 MID/RID value of SSI tx1 = 0x259
70 MID/RID value of SSI rt2 = 0x25f
71 MID/RID value of SSI rx3 = 0x262
72 MID/RID value of SSI tx3 = 0x261
75 bit[11] - LVL = 0, Detects based on the edge
77 bit[15] - TM = 0, Single transfer mode
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043.dtsi17 #clock-cells = <0>;
19 clock-frequency = <0>;
24 #clock-cells = <0>;
26 clock-frequency = <0>;
32 #clock-cells = <0>;
33 clock-frequency = <0>;
39 #clock-cells = <0>;
41 clock-frequency = <0>;
44 cluster0_opp: opp-table-0 {
80 reg = <0 0x10001200 0 0xb00>;
[all …]
H A Dr9a07g054.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]
H A Dr9a07g044.dtsi18 #clock-cells = <0>;
20 clock-frequency = <0>;
25 #clock-cells = <0>;
27 clock-frequency = <0>;
33 #clock-cells = <0>;
34 clock-frequency = <0>;
40 #clock-cells = <0>;
42 clock-frequency = <0>;
45 cluster0_opp: opp-table-0 {
74 #size-cells = <0>;
[all …]