Searched +full:0 +full:x10048000 (Results 1 – 6 of 6) sorted by relevance
| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,exynos4412-isp-clock.yaml | 58 reg = <0x10048000 0x1000>;
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| /linux/Documentation/devicetree/bindings/pwm/ |
| H A D | renesas,rzg2l-gpt.yaml | 269 reg = <0x10048000 0x800>;
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | exynos4x12.dtsi | 70 #interconnect-cells = <0>; 80 #interconnect-cells = <0>; 120 #interconnect-cells = <0>; 211 reg = <0x11400000 0x1000>; 217 reg = <0x11000000 0x1000>; 229 reg = <0x03860000 0x1000>; 231 interrupts = <10 0>; 236 reg = <0x106e0000 0x1000>; 242 reg = <0x02020000 0x40000>; 245 ranges = <0 0x02020000 0x40000>; [all …]
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| /linux/drivers/net/ethernet/microchip/sparx5/ |
| H A D | sparx5_main.c | 53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */ 54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ 55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */ 56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */ 57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */ 58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */ 59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */ 60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */ 61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */ 62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */ [all …]
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r9a07g054.dtsi | 18 #clock-cells = <0>; 20 clock-frequency = <0>; 25 #clock-cells = <0>; 27 clock-frequency = <0>; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 40 #clock-cells = <0>; 42 clock-frequency = <0>; 45 cluster0_opp: opp-table-0 { 74 #size-cells = <0>; [all …]
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| H A D | r9a07g044.dtsi | 18 #clock-cells = <0>; 20 clock-frequency = <0>; 25 #clock-cells = <0>; 27 clock-frequency = <0>; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 40 #clock-cells = <0>; 42 clock-frequency = <0>; 45 cluster0_opp: opp-table-0 { 74 #size-cells = <0>; [all …]
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